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AD8067 데이터시트 PDF




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AD8067 데이터시트, 핀배열, 회로
Data Sheet
FEATURES
FET input amplifier: 0.6 pA input bias current
Stable for gains ≥8
High speed
54 MHz, −3 dB bandwidth (G = +10)
640 V/µs slew rate
Low noise
6.6 nV/√Hz
0.6 fA/√Hz
Low offset voltage (1.0 mV max)
Wide supply voltage range: 5 V to 24 V
No phase reversal
Low input capacitance
Single-supply and rail-to-rail output
Excellent distortion specs: SFDR 95 dBc @ 1 MHz
High common-mode rejection ratio: −106 dB
Low power: 6.5 mA typical supply current
Low cost
Small packaging: SOT-23-5
APPLICATIONS
Photodiode preamplifiers
Precision high gain amplifiers
High gain, high bandwidth composite amplifiers
GENERAL DESCRIPTION
The AD8067 FastFET amp is a voltage feedback amplifier with
FET inputs offering wide bandwidth (54 MHz @ G = +10) and
high slew rate (640 V/µs). The AD8067 is fabricated in a
proprietary, dielectrically isolated eXtra Fast Complementary
Bipolar process (XFCB) that enables high speed, low power, and
high performance FET input amplifiers.
The AD8067 is designed to work in applications that require
high speed and low input bias current, such as fast photodiode
preamplifiers. As required by photodiode applications, the laser
trimmed AD8067 has excellent dc voltage offset (1.0 mV max)
and drift (15 µV/°C max).
The FET input bias current (5 pA max) and low voltage noise
(6.6 nV/√Hz) also contribute to making it appropriate for precision
applications. With a wide supply voltage range (5 V to 24 V)
and rail-to-rail output, the AD8067 is well suited for a variety of
applications that require wide dynamic range and low distortion.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
High Gain Bandwidth Product,
Precision Fast FETOp Amp
AD8067
CONNECTION DIAGRAM (TOP VIEW)
SOT-23-5 (RT-5)
VOUT 1
5 +VS
–VS 2
+IN 3
Figure 1.
4 –IN
The AD8067 amplifier is available in a SOT-23-5 package and is
rated to operate over the industrial temperature range of –40°C
to +85°C.
28
G = +20
26
24
22
G = +10
20
18
G = +8
16
14
12
10
8
0.1 1 10
FREQUENCY – MHz
Figure 2. Small Signal Frequency Response
100
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2002–2012 Analog Devices, Inc. All rights reserved.




AD8067 pdf, 반도체, 판매, 대치품
Data Sheet
AD8067
SPECIFICATIONS FOR ±5 V
VS = ±5 V (@ TA = +25°C, G = +10, RF = RL =1 kΩ, unless otherwise noted.)
Table 1.
Parameter
Conditions
DYNAMIC PERFORMANCE
−3 dB Bandwidth
Bandwidth for 0.1 dB Flatness
Output Overdrive Recovery Time (Pos/Neg)
Slew Rate
Settling Time to 0.1%
NOISE/DISTORTION PERFORMANCE
Spurious-Free Dynamic Range (SFDR)
Input Voltage Noise
Input Current Noise
VO = 0.2 V p-p
VO = 2 V p-p
VO = 0.2 V p-p
VI = ±0.6 V
VO = 5 V step
VO = 5 V step
fC = 1 MHz, 2 V p-p
fC = 1 MHz, 8 V p-p
fC = 5 MHz, 2 V p-p
fC = 1 MHz, 2 V p-p, RL = 150 Ω
f = 10 kHz
f = 10 kHz
DC PERFORMANCE
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current
Input Offset Current
Open-Loop Gain
INPUT CHARACTERISTICS
TMIN to TMAX
TMIN to TMAX
VO = ±3 V
Common-Mode Input Impedance
Differential Input Impedance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio (CMRR)
OUTPUT CHARACTERISTICS
Output Voltage Swing
Output Current
Short Circuit Current
Capacitive Load Drive
VCM = –1 V to +1 V
RL = 1 kΩ
RL = 150 Ω
SFDR > 60 dBc, f = 1 MHz
30% overshoot
POWER SUPPLY
Operating Range
Quiescent Current
Power Supply Rejection Ratio (PSRR)
Min Typ Max Unit
39 54
54
8
115/190
500 640
27
MHz
MHz
MHz
ns
V/µs
ns
95 dBc
84 dBc
82 dBc
72 dBc
6.6 nV/√Hz
0.6 fA/√Hz
0.2 1.0 mV
1 15 µV/°C
0.6 5 pA
25 pA
0.2 1 pA
1 pA
103 119
dB
1000||1.5
GΩ||pF
1000||2.5
GΩ||pF
−5.0 2.0 V
−85 −106
dB
−4.86 to +4.83
−4.92 to +4.92
−4.67 to +4.72
30
105
120
V
V
mA
mA
pF
5 24 V
6.5 6.8 mA
−90 −109
dB
Rev. B | Page 3 of 24

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AD8067 전자부품, 판매, 대치품
AD8067
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter
Supply Voltage
Power Dissipation
Common-Mode Input Voltage
Differential Input Voltage
Storage Temperature Range
Operating Temperature Range
Lead Temperature (Soldering 10 sec)
Junction Temperature
Rating
26.4 V
See Figure 3
VEE – 0.5 V to VCC + 0.5 V
1.8 V
–65°C to +125°C
–40°C to +85°C
300°C
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
MAXIMUM POWER DISSIPATION
The associated raise in junction temperature (TJ) on the die
limits the maximum safe power dissipation in the AD8067
package. At approximately 150°C, which is the glass transition
temperature, the plastic changes its properties. Even temporarily
exceeding this temperature limit can change the stresses that the
package exerts on the die, permanently shifting the parametric
performance of the AD8067. Exceeding a junction temperature
of 175°C for an extended period can result in changes in the
silicon devices, potentially causing failure.
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive. The quiescent power is the
voltage between the supply pins (VS) times the quiescent
current (IS). Assuming the load (RL) is referenced to midsupply,
the total drive power is VS/2 × IOUT, some of which is dissipated
in the package and some in the load (VOUT × IOUT). The
difference between the total drive power and the load power is
the drive power dissipated in the package. RMS output voltages
should be considered.
Data Sheet
PD = Quiescent Power + (Total Drive Power Load Power)
( )PD =
VS × IS
+

VS
2
×
VOUT
RL

VOUT
RL
2
If RL is referenced to VS− as in single-supply operation, then the
total drive power is VS × IOUT.
If the rms signal levels are indeterminate, then consider the
worst case, when VOUT = VS/4 for RL to midsupply:
PD
= (VS
×IS )
+
(VS/4)2
RL
In single-supply operation with RL referenced to VS−, worst case
is VOUT = VS/2.
Airflow increases heat dissipation effectively, reducing θJA. In
addition, more metal directly in contact with the package leads
from metal traces, through holes, ground, and power planes
reduces the θJA.
Figure 3 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the SOT-23-5
(180°C/W) package on a JEDEC standard 4-layer board. θJA
values are approximations.
It should be noted that for every 10°C rise in temperature, IB
approximately doubles (see Figure 22).
2.0
1.5
1.0
SOT-23-5
0.5
0
–40 –30 –20 –10 0 10 20 30 40 50 60 70 80
AMBIENT TEMPERATURE – °C
Figure 3. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. B | Page 6 of 24

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