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PDF AD8109 Data sheet ( Hoja de datos )
| Número de pieza | AD8109 | |
| Descripción | 8 x 8 Buffered Video Crosspoint Switches | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Data Sheet
FEATURES
8 × 8 high speed nonblocking switch arrays
AD8108: G = 1
AD8109: G = 2
Serial or parallel programming of switch array
Serial data out allows daisy-chaining of multiple 8 × 8 arrays
to create larger switch arrays
Output disable allows connection of multiple devices
Pin-compatible with AD8110/AD8111 16 × 8 switch arrays
For 16 × 16 arrays see AD8116
Complete solution
Buffered inputs
Eight output amplifiers
AD8108 (G = 1)
AD8109 (G = 2)
Drives 150 Ω loads
Excellent video performance
60 MHz 0.1 dB gain flatness
0.02%/0.02° differential gain/differential phase error
(RL = 150 Ω)
Excellent ac performance
−3 dB bandwidth: 325 MHz (AD8108), 250 MHz (AD8109)
Slew rate: 400 V/µs (AD8108), 480 V/µs (AD8109)
Low power of 45 mA
Low all hostile crosstalk of −83 dB at 5 MHz
Reset pin allows disabling of all outputs (connected through
a capacitor to ground provides power-on reset capability)
Excellent ESD rating: exceeds 4000 V human body model
80-lead LQFP (12 mm × 12 mm)
APPLICATIONS
Routing of high speed signals including
Composite video (NTSC, PAL, S, SECAM)
Component video (YUV, RGB)
Compressed video (MPEG, Wavelet)
3-level digital video (HDB3)
GENERAL DESCRIPTION
The AD8108/AD8109 are high speed 8 × 8 video crosspoint
switch matrices. They offer a −3 dB signal bandwidth greater than
250 MHz and channel switch times of less than 25 ns with 1%
settling. With −83 dB of crosstalk and −98 dB isolation (at 5 MHz),
the AD8108/AD8109 are useful in many high speed applications.
The differential gain and differential phase of better than 0.02%
325 MHz, 8 × 8 Buffered Video
Crosspoint Switches
AD8108/AD8109
FUNCTIONAL BLOCK DIAGRAM
SER/PAR D0 D1 D2 D3
CLK
DATA IN
UPDATE
CE
RESET
A0
A1
A2
32-BIT SHIFT REGISTER
WITH 4-BIT
PARALLEL LOADING
32
PARALLEL LATCH
32
DECODE
8 × 4:8 DECODERS
SET INDIVIDUAL
OR RESET ALL
OUTPUTS
TO "OFF"
8
DATA
OUT
AD8108/AD8109
64
OUTPUT
BUFFER
G = +1
G = +2
8 INPUTS
SWITCH
MATRIX
8 OUTPUTS
Figure 1. Functional Block Diagram
and 0.02°, respectively, along with 0.1 dB flatness out to 60 MHz,
make the AD8108/AD8109 ideal for video signal switching.
The AD8108 and AD8109 include eight independent output
buffers that can be placed into a high impedance state for paral-
leling crosspoint outputs so that off channels do not load the
output bus. The AD8108 has a gain of 1, while the AD8109
offers a gain of 2. They operate on voltage supplies of ±5 V
while consuming only 45 mA of idle current. The channel
switching is performed via a serial digital control (which can
accommodate daisy-chaining of several devices) or via a parallel
control allowing updating of an individual output without
reprogramming the entire array.
The AD8108/AD8109 is packaged in an 80-lead LQFP and is
available over the extended industrial temperature range of
−40°C to +85°C.
Rev. C
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©1997–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
Data Sheet
TIMING CHARACTERISTICS (SERIAL)
Table 2. Timing Characteristics
Parameter
Serial Data Setup Time
CLK Pulse Width
Serial Data Hold Time
CLK Pulse Separation, Serial Mode
CLK to UPDATE Delay
UPDATE Pulse Width
CLK to DATA OUT Valid, Serial Mode
Propagation Delay, UPDATE to Switch On or Off
Data Load Time, CLK = 5 MHz, Serial Mode
CLK, UPDATE Rise and Fall Times
RESET Time
AD8108/AD8109
Symbol
t1
t2
t3
t4
t5
t6
t7
–
–
–
–
Min Typ Max Unit
20 ns
100 ns
20 ns
100 ns
0 ns
50 ns
180 ns
8 ns
6.4 µs
100 ns
200 ns
Table 3. Logic Levels
VIH
RESET, SER/PAR
CLK, DATA IN,
CE, UPDATE
VIL
RESET, SER/PAR
CLK, DATA IN,
CE, UPDATE
2.0 V min
0.8 V max
VOH
DATA OUT
2.7 V min
VOL
DATA OUT
0.5 V max
IIH
RESET, SER/PAR
CLK, DATA IN,
CE, UPDATE
20 µA max
IIL
RESET, SER/PAR
CLK, DATA IN,
CE, UPDATE
−400 µA min
IOH
DATA OUT
−400 µA max
IOL
DATA OUT
3.0 mA min
1
CLK
0
1
DATA IN
0
1 = LATCHED
UPDATE
0 = TRANSPARENT
DATA OUT
t2
t1 t3
OUT7 (D3)
t7
t4
LOAD DATA INTO
SERIAL REGISTER
ON FALLING EDGE
OUT7 (D2)
OUT00 (D0)
t5
TRANSFER DATA FROM SERIAL
REGISTER TO PARALLEL
LATCHES DURING LOW LEVEL
t6
Figure 2. Timing Diagram, Serial Mode
Rev. C | Page 5 of 27
5 Page 
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
5
RL = 150
4
0.4
0.3
3 0.2
2 0.1
FLATNESS
1
0
0
GAIN
200mV p-p
–0.1
–1 –0.2
2V p-p
–2 –0.3
–3
100k
1M 10M 100M
FREQUENCY (Hz)
–0.4
1G
Figure 7. AD8108 Frequency Response
AD8108/AD8109
+50mV
+25mV
0
–25mV
–50mV
10ns/DIV
Figure 10. AD8108 Step Response, 100 mV Step
–10
RL = 1k
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
0.2
1
ALL HOSTILE
ADJACENT
10
FREQUENCY (MHz)
100 200
Figure 8. AD8108 Crosstalk vs. Frequency
+1.0V
+0.5V
0
–0.5V
–1.0V
10ns/DIV
Figure 11. AD8108 Step Response, 2 V Step
–30
RL = 150
VOUT = 2V p-p
–40
–50
2ND HARMONIC
–60
–70
–80
3RD HARMONIC
–90
–100
100k
1M 10M
FREQUENCY (Hz)
Figure 9. AD8108 Distortion vs. Frequency
100M
0.2
0.1
0
–0.1
–0.2
2V STEP
RL=150
0 10 20 30 40 50 60 70 80
10ns/DIV
Figure 12. AD8108 Settling Time
Rev. C | Page 11 of 27
11 Page | ||
| Páginas | Total 27 Páginas | |
| PDF Descargar | [ Datasheet AD8109.PDF ] | |
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