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AD8110 데이터시트 PDF




Analog Devices에서 제조한 전자 부품 AD8110은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


PDF 형식의 AD8110 자료 제공

부품번호 AD8110 기능
기능 16 x 8 Buffered Video Crosspoint Switches
제조업체 Analog Devices
로고 Analog Devices 로고


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AD8110 데이터시트, 핀배열, 회로
a
260 MHz, 16 ؋ 8 Buffered
Video Crosspoint Switches
AD8110/AD8111
FEATURES
16 ؋ 8 High-Speed Nonblocking Switch Arrays
AD8110: G = +1
AD8111: G = +2
Serial or Parallel Switch Array Control
Serial Data Out Allows “Daisy Chaining” of Multiple
Crosspoints to Create Larger Switch Arrays
Pin-Compatible with AD8108/AD8109 8 ؋ 8 Switch
Arrays
For a 16 ؋ 16 Array See AD8116
Complete Solution
Buffered Inputs
Eight Output Amplifiers, AD8110 (G = +1),
AD8111 (G = +2)
Drives 150 V Loads
Excellent Video Performance
60 MHz 0.1 dB Gain Flatness
0.02% Differential Gain Error (RL = 150 V)
0.028 Differential Phase Error (RL = 150 V)
Excellent AC Performance
260 MHz –3 dB Bandwidth
500 V/ms Slew Rate
Low Power of 50 mA
Low All Hostile Crosstalk of –78 dB @ 5 MHz
Output Disable Allows Direct Connection of Multiple
Device Outputs
Reset Pin Allows Disabling of All Outputs (Connected
Through a Capacitor to Ground Provides “Power-
On” Reset Capability)
Excellent ESD Rating: Exceeds 4000 V Human Body
Model
80-Lead LQFP Package (12 mm ؋ 12 mm)
APPLICATIONS
Routing of High-Speed Signals Including:
Composite Video (NTSC, PAL, S, SECAM)
Component Video (YUV, RGB)
Compressed Video (MPEG, Wavelet)
3-Level Digital Video (HDB3)
PRODUCT DESCRIPTION
The AD8110 and AD8111 are high-speed 16 × 8 video cross-
point switch matrices. They offer a –3 dB signal bandwidth
greater than 260 MHz, and channel switch times of less than
25 ns with 1% settling. With –78 dB of crosstalk and –97 dB
isolation (@ 5 MHz), the AD8110/AD8111 are useful in many
high-speed applications. The differential gain and differential
FUNCTIONAL BLOCK DIAGRAM
SER/PAR D0 D1 D2 D3 D4
CLK
DATA IN
UPDATE
CE
RESET
A0
A1
A2
40-BIT SHIFT REGISTER
WITH 5-BIT
PARALLEL LOADING
40
PARALLEL LATCH
40
DECODE
8 ؋ 5:16 DECODERS
SET INDIVIDUAL
OR RESET ALL
OUTPUTS
TO "OFF"
8
DATA
OUT
AD8110/AD8111
OUTPUT
128 BUFFER
G = +1,
G = +2
16 INPUTS
SWITCH
MATRIX
8 OUTPUTS
phase of better than 0.02% and 0.02° respectively, along with
0.1 dB flatness out to 60 MHz, make the AD8110/AD8111
ideal for video signal switching.
The AD8110 and AD8111 include eight independent output
buffers that can be placed into a high impedance state for paral-
leling crosspoint outputs so that off channels do not load the
output bus. The AD8110 has a gain of +1, while the AD8111
offers a gain of +2. They operate on voltage supplies of ±5 V
while consuming only 50 mA of idle current. The channel
switching is performed via a serial digital control (which can
accommodate “daisy chaining” of several devices) or via a parallel
control, allowing updating of an individual output without repro-
gramming the entire array.
The AD8110/AD8111 is packaged in an 80-lead LQFP package
and is available over the extended industrial temperature range
of –40°C to +85°C.
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com




AD8110 pdf, 반도체, 판매, 대치품
AD8110/AD8111
TIMING CHARACTERISTICS (Parallel)
Parameter
Data Setup Time
CLK Pulsewidth
Data Hold Time
CLK Pulse Separation
CLK to UPDATE Delay
UPDATE Pulsewidth
Propagation Delay, UPDATE to Switch On or Off
CLK, UPDATE Rise and Fall Times
RESET Time
Symbol
t1
t2
t3
t4
t5
t6
Limit
Min Max
20
100
20
100
0
50
8
100
200
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
CLK
0
1
D0–D4
A0–A2
0
1 = LATCHED
UPDATE
0 = TRANSPARENT
t2
t1 t3
t4
Figure 2. Timing Diagram, Parallel Mode
t5 t6
Table II. Logic Levels
VIH
RESET, SER/PAR
CLK, D0, D1, D2,
D3, D4, A0, A1, A2
CE, UPDATE
VIL VOH
RESET, SER/PAR
CLK, D0, D1, D2,
D3, D4, A0, A1, A2
CE, UPDATE
DATA OUT
VOL
DATA OUT
2.0 V min
0.8 V max
2.7 V min 0.5 V max
IIH
RESET, SER/PAR
CLK, D0, D1, D2,
D3, D4, A0, A1, A2
CE, UPDATE
IIL
RESET, SER/PAR
CLK, D0, D1, D2,
D3, D4, A0, A1, A2
CE, UPDATE
IOH
DATA OUT
20 μA max
–400 μA min
–400 μA max
IOL
DATA OUT
3.0 mA min
–4– 3&7#

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AD8110 전자부품, 판매, 대치품
AD8110/AD8111
Pin Name
INxx
DATA IN
CLK
DATA OUT
UPDATE
Pin Numbers
66, 68, 70, 72, 74, 76, 78,
1, 3, 5, 7, 9, 11, 13, 15, 64
57
58
59
56
RESET
CE
SER/PAR
OUTyy
AGND
DVCC
DGND
AVEE
AVCC
AGNDxx
AVCCxx/yy
AVEExx/yy
A0
A1
A2
D0
D1
D2
D3
D4
61
60
55
41, 38, 35, 32, 29, 26, 23, 20
2, 4, 6, 8, 10, 12, 14, 16, 46
65, 67, 69, 71, 73, 75, 77
63, 79
62, 80
17, 45
18, 44
42, 39, 36, 33, 30, 27, 24, 21
43, 37, 31, 25, 22, 19
40, 34, 28, 22
54
53
52
51
50
49
48
47
PIN FUNCTION DESCRIPTIONS
Pin Description
Analog Inputs; xx = Channel Numbers 00 Through 15.
Serial Data Input, TTL Compatible.
Clock, TTL Compatible. Falling Edge Triggered.
Serial Data Out, TTL Compatible.
Enable (Transparent) “Low.” Allows serial register to connect directly to switch
matrix. Data latched when “High.”
Disable Outputs, Active “Low.”
Chip Enable, Enable “Low.” Must be “low” to clock in and latch data.
Selects Serial Data Mode, “Low” or Parallel Data Mode, “High.” Must be connected.
Analog Outputs yy = Channel Numbers 00 Through 07.
Analog Ground for Inputs and Switch Matrix.
5 V for Digital Circuitry.
Ground for Digital Circuitry.
–5 V for Inputs and Switch Matrix.
+5 V for Inputs and Switch Matrix.
Ground for Output Amp, xx = Output Channel Numbers 00 Through 07. Must be connected.
+5 V for Output Amplifier that is shared by Channel Numbers xx and yy. Must be connected.
–5 V for Output Amplifier that is shared by Channel Numbers xx and yy. Must be connected.
Parallel Data Input, TTL Compatible (Output Select LSB).
Parallel Data Input, TTL Compatible (Output Select).
Parallel Data Input, TTL Compatible (Output Select MSB).
Parallel Data Input, TTL Compatible (Input Select LSB).
Parallel Data Input, TTL Compatible (Input Select).
Parallel Data Input, TTL Compatible (Input Select).
Parallel Data Input, TTL Compatible (Input Select MSB).
Parallel Data Input, TTL Compatible (Output Enable).
VCC
ESD
INPUT
ESD
AVEE
a. Analog Input
VCC
ESD
ESD
OUTPUT
1k
(AD8111 ONLY)
AVEE
b. Analog Output
VCC
ESD
RESET
ESD
20k
DGND
c. Reset Input
VCC
ESD
INPUT
ESD
VCC
2k
ESD
ESD
OUTPUT
DGND
d. Logic Input
DGND
e. Logic Output
Figure 5. I/O Schematics
3&7#
–7–

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