AD8114 Datasheet PDF - Analog Devices
| Part Number | AD8114 | |
| Description | 16 x 16 Crosspoint Switches | |
| Manufacturers | Analog Devices | |
| Logo |  |
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Data Sheet
FEATURES
16 × 16 high speed nonblocking switch arrays
AD8114; G = 1
AD8115; G = 2
Serial or parallel programming of switch array
Serial data out allows daisy-chaining of multiple
16 × 16 arrays to create larger switch arrays
High impedance output disable allows connection of
multiple devices without loading the output bus
For smaller arrays see the AD8108/AD8109 (8 × 8) or
AD8110/AD8111 (16 × 8) switch arrays
Complete solution
Buffered inputs
Programmable high impedance outputs
16 output amplifiers, AD8114 (G = 1), AD8115 (G = 2)
Drives 150 Ω loads
Excellent video performance
25 MHz, 0.1 dB gain flatness
0.05%/0.05° differential gain/differential phase error
(RL = 150 Ω)
Excellent ac performance
−3 dB bandwidth: 225 MHz
Slew rate: 375 V/µs
Low power of 700 mW (2.75 mW per point)
Low all hostile crosstalk of −70 dB at 5 MHz
Reset pin allows disabling of all outputs (connected through
a capacitor to ground provides power-on reset capability)
100-lead LQFP (14 mm × 14 mm)
APPLICATIONS
Routing of high speed signals, including
Video (NTSC, PAL, S, SECAM, YUV, RGB)
Compressed video (MPEG, wavelet)
3-level digital video (HDB3)
Data communications
Telecommunications
GENERAL DESCRIPTION
The AD8114/AD8115 are high speed, 16 × 16 video crosspoint
switch matrices. They offer a −3 dB signal bandwidth greater than
200 MHz and channel switch times of less than 50 ns with 1%
settling. With −70 dB of crosstalk and −98 dB isolation (at 5 MHz),
the AD8114/AD8115 are useful in many high speed applications.
Low Cost, 225 MHz,
16 × 16 Crosspoint Switches
AD8114/AD8115
FUNCTIONAL BLOCK DIAGRAM
SER/PAR D0 D1 D2 D3 D4
CLK
DATA IN
UPDATE
CE
RESET
80-BIT SHIFT REGISTER
WITH 5-BIT
PARALLEL LOADING
A0
A1
A2
A3
DATA
OUT
80
PARALLEL LATCH
80
DECODE
16 × 5:16 DECODERS
SET
INDIVIDUAL
OR RESET
ALL OUTPUTS
TO "OFF"
16
AD8114/AD8115
OUTPUT
256 BUFFER
G = +1,
G = +2
16 INPUTS
SWITCH
MATRIX
16
OUTPUTS
Figure 1.
The differential gain and differential phase of better than 0.05%
and 0.05°, respectively, along with a 0.1 dB flatness out to 25 MHz
while driving a 75 Ω back-terminated load, make the AD8114/
AD8115 ideal for all types of signal switching.
The AD8114/AD8115 include 16 independent output buffers
that can be placed into a high impedance state for paralleling
crosspoint outputs so that off channels do not load the output bus.
The AD8114 has a gain of 1, while the AD8115 offers a gain of 2.
They operate on voltage supplies of ±5 V while consuming only
70 mA of idle current. The channel switching is performed via a
serial digital control (which can accommodate daisy-chaining of
several devices) or via a parallel control, allowing updating of an
individual output without reprogramming the entire array.
The AD8114/AD8115 is packaged in a 100-lead LQFP and is
available over the extended industrial temperature range of
−40°C to +85°C.
Rev. C
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©1998–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
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Data Sheet
TIMING CHARACTERISTICS (SERIAL)
Table 2. Timing Characteristics
Parameter
Serial Data Setup Time
CLK Pulse Width
Serial Data Hold Time
CLK Pulse Separation, Serial Mode
CLK to UPDATE Delay
UPDATE Pulse Width
CLK to DATA OUT Valid, Serial Mode
Propagation Delay, UPDATE to Switch On or Off
Data Load Time, CLK = 5 MHz, Serial Mode
CLK, UPDATE Rise and Fall Times
RESET Time
AD8114/AD8115
Symbol
t1
t2
t3
t4
t5
t6
t7
Min Typ Max Unit
20 ns
100 ns
20 ns
100 ns
0 ns
50 ns
200 ns
50 ns
16 µs
100 ns
200 ns
Table 3. Logic Levels
VIH VIL
RESET, SER/PAR
CLK, DATA IN,
CE, UPDATE
RESET, SER/PAR
CLK, DATA IN,
CE, UPDATE
2.0 V min
0.8 V max
VOH
DATA OUT
2.7 V min
VOL
DATA OUT
0.5 V max
IIH
RESET, SER/PAR
CLK, DATA IN,
CE, UPDATE
20 µA max
IIL
RESET, SER/PAR
CLK, DATA IN,
CE, UPDATE
−400 µA min
IOH
DATA OUT
−400 µA max
IOL
DATA OUT
3.0 mA min
1
CLK
0
1
DATA IN
0
1 = LATCHED
UPDATE
0 = TRANSPARENT
DATA OUT
t2
t1 t3
OUT7 (D4)
t7
t4
LOAD DATA INTO
SERIAL REGISTER
ON FALLING EDGE
OUT7 (D3)
OUT00 (D0)
t5
TRANSFER DATA FROM SERIAL
REGISTER TO PARALLEL
LATCHES DURING LOW LEVEL
t6
Figure 2. Timing Diagram, Serial Mode
Rev. C | Page 5 of 25
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Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for AD8114 electronic component. |
| Information | Total 25 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
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| Download | [ AD8114.PDF Datasheet ] | |
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