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PDF AD8306 Data sheet ( Hoja de datos )

Número de pieza AD8306
Descripción 5MHz - 400MHz 100dB High Precision Limiting-Logarithmic Amplifier
Fabricantes Analog Devices 
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a
5 MHz–400 MHz 100 dB High Precision
Limiting-Logarithmic Amplifier
AD8306
FEATURES
Complete, Fully Calibrated Log-Limiting IF Amplifier
100 dB Dynamic Range: –91 dBV to +9 dBV
Stable RSSI Scaling Over Temperature and Supplies:
20 mV/dB Slope, –95 dBm Intercept
؎0.4 dB RSSI Linearity up to 200 MHz
Programmable Limiter Gain and Output Current
Differential Outputs to 10 mA, 2.4 V p-p
Overall Gain 90 dB, Bandwidth 400 MHz
Constant Phase (Typical ؎56 ps Delay Skew)
Single Supply of +2.7 V to +6.5 V at 16 mA Typical
Fully Differential Inputs, RIN = 1 k, CIN = 2.5 pF
500 ns Power-Up Time, <1 A Sleep Current
APPLICATIONS
Receivers for Frequency and Phase Modulation
Very Wide Range IF and RF Power Measurement
Receiver Signal Strength Indication (RSSI)
Low Cost Radar and Sonar Signal Processing
Instrumentation: Network and Spectrum Analyzers
FUNCTIONAL BLOCK DIAGRAM
SIX STAGES TOTAL GAIN 72dB
TYP GAIN 18dB
INHI
INLO
12dB
LADR ATTEN
4 ؋ DET
DET
12dB
DET
12dB
LIM
DET
BIAS
CTRL
LMHI
LMLO
LMDR
TEN DETECTORS SPACED 12dB
I–V VLOG
FLTR
ENBL
GAIN
BIAS
BAND-GAP
REFERENCE
SLOPE
BIAS
INTERCEPT
TEMP COMP
PRODUCT DESCRIPTION
The AD8306 is a complete IF limiting amplifier, providing both
an accurate logarithmic (decibel) measure of the input signal
(the RSSI function) over a dynamic range of 100 dB, and a
programmable limiter output, useful from 5 MHz to 400 MHz.
It is easy to use, requiring few external components. A single
supply voltage of +2.7 V to +6.5 V at 16 mA is needed, corre-
sponding to a power consumption of under 50 mW at 3 V, plus
the limiter bias current, determined by the application and typi-
cally 2 mA, providing a limiter gain of 90 dB when using 200
loads. A CMOS-compatible control interface can enable the
AD8306 within about 500 ns and disable it to a standby current
of under 1 µA.
The six cascaded amplifier/limiter cells in the main path have a
small signal gain of 12.04 dB (×4), with a –3 dB bandwidth of
850 MHz, providing a total gain of 72 dB. The programmable
output stage provides a further 18 dB of gain. The input is fully
differential and presents a moderately high impedance (1 kin
parallel with 2.5 pF). The input-referred noise-spectral-density,
when driven from a terminated 50 , source is 1.28 nV/Hz,
equivalent to a noise figure of 3 dB. The sensitivity of the
AD8306 can be raised by using an input matching network.
Each of the main gain cells includes a full-wave detector. An
additional four detectors, driven by a broadband attenuator, are
used to extend the top end of the dynamic range by over 48 dB.
The overall dynamic range for this combination extends from
–91 dBV (–78 dBm at the 50 level) to a maximum permissible
value of +9 dBV, using a balanced drive of antiphase inputs each of
2 V in amplitude, which would correspond to a sine wave power
of +22 dBm if the differential input were terminated in 50 .
Through laser trimming, the slope of the RSSI output is closely
controlled to 20 mV/dB, while the intercept is set to –108 dBV
(–95 dBm re 50 ). These scaling parameters are determined
by a band-gap voltage reference and are substantially indepen-
dent of temperature and supply. The logarithmic law conform-
ance is typically within ± 0.4 dB over the central 80 dB of this
range at any frequency between 10 MHz and 200 MHz, and is
degraded only slightly at 400 MHz.
The RSSI response time is nominally 73 ns (10%–90%). The
averaging time may be increased without limit by the addition of
an external capacitor. The full output of 2.34 V at the maximum
input of +9 dBV can drive any resistive load down to 50 and
this interface remains stable with any value of capacitance on
the output.
The AD8306 is fabricated on an advanced complementary
bipolar process using silicon-on-insulator isolation techniques
and is available in the industrial temperature range of –40°C to
+85°C, in a 16-lead narrow body SO package. The AD8306 is
also available for the full military temperature range of –55°C to
+125°C, in a 16-lead side-brazed ceramic DIP.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999

1 page




AD8306 pdf
AD8306–Typical Performance Characteristics
100
10
1
TA = +25؇C
0.1
TA = +85؇C
0.01
TA = –40؇C
0.001
0.0001
0.00001
0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5
ENABLE VOLTAGE – V
Figure 1. Supply Current vs. Enable Voltage @
TA = –40°C, +25°C and +85°C
500mV PER
VERTICAL
DIVISION
VLOG
GROUND REFERENCE
INPUT LEVEL
SHOWN IS –3dBV
INPUT
100ns PER HORIZONTAL DIVISION
1V PER
VERTICAL
DIVISION
Figure 4. RSSI Pulse Response for Inputs Stepped from
Zero to –83 dBV, –63 dBV, –43 dBV, –23 dBV, –3 dBV
14
12
10
ADDITIONAL SUPPLY CURRENT
8
6
4
2
LIMITER OUTPUT
CURRENT
0
0 50 100 150 200 250 300 350 400 450
RLIM
Figure 2. Additional Supply Current and Limiter Output
Current vs. RLIM
500mV PER
VERTICAL
DIVISION
VLOG
GROUND REFERENCE
INPUT
2V PER
VERTICAL
DIVISION
100ns PER HORIZONTAL DIVISION
Figure 5. Large Signal RSSI Pulse Response with RL = 100
and CL = 33 pF, 100 pF and 330 pF (Overlapping Curves)
500mV PER
VERTICAL
DIVISION
VLOG
GROUND REFERENCE
INPUT
2V PER
VERTICAL
DIVISION
100ns PER HORIZONTAL DIVISION
Figure 3. Large Signal RSSI Pulse Response with
CL = 100 pF and RL = 50 and 75 (Curves Overlap)
27pF
270pF
200mV PER
VERTICAL
DIVISION
3300pF
VLOG
GROUND REFERENCE
100s PER HORIZONTAL DIVISION
Figure 6. Small Signal AC Response of RSSI Output with
External Filter Capacitance of 27 pF, 270 pF and 3300 pF
–4– REV. A

5 Page





AD8306 arduino
AD8306
low frequency applications, a simple RC network forming a low-
pass filter should be added at the input for the same reason.
If the limiter output is not required, Pin 9 (LMDR) should be
left open and Pins 12 and 13 (LMHI, LMLO) should be tied to
VPS2 as shown in Figure 24.
Figure 25 shows the output versus the input level in dBV, for
sine inputs at 10 MHz, 50 MHz and 100 MHz (add 13 to the
dBV number to get dBm Re 50 . Figure 26 shows the typi-
cal logarithmic linearity (log conformance) under the same
conditions.
2.5
100MHz
2
50MHz
10MHz
1.5
1
0.5
0
–120
–100
–80 –60 –40 –20
INPUT LEVEL – dBV
0
20
Figure 25. RSSI Output vs. Input Level at TA = +25°C for
Frequencies of 10 MHz, 50 MHz and 100 MHz
5
DYNAMIC RANGE ؎1dB ؎3dB
4
10MHz
86 93
50MHz
90 97
3
100MHz
96 100
2
1
100MHz
0
10MHz
–1
50MHz
–2
–3
–4
–5
–120
–100
–80 –60 –40 –20
INPUT LEVEL – dBV
0
20
Figure 26. Log Linearity vs. Input Level at TA = +25°C, for
Frequencies of 10 MHz, 50 MHz and 100 MHz
Transfer Function in Terms of Slope and Intercept
The transfer function of the AD8306 is characterized in terms
of its Slope and Intercept. The logarithmic slope is defined as
the change in the RSSI output voltage for a 1 dB change at the
input. For the AD8306 the slope is calibrated to be 20 mV/dB.
The intercept is the point at which the extrapolated linear re-
sponse would intersect the horizontal axis. For the AD8306 the
intercept is calibrated to be –108 dBV (–95 dBm). Using the
slope and intercept, the output voltage can be calculated for any
input level within the specified input range using the equation:
VOUT = VSLOPE × (PIN PO)
(2)
where VOUT is the demodulated and filtered RSSI output,
VSLOPE is the logarithmic slope, expressed in V/dB, PIN is the
input signal, expressed in decibels relative to some reference
level (either dBm or dBV in this case) and PO is the logarithmic
intercept, expressed in decibels relative to the same reference
level.
For example, for an input level of –33 dBV (–20 dBm), the
output voltage will be
VOUT = 0.02 V/dB × (–33 dBV – (–108 dBV)) = 1.5 V (3)
The most widely used convention in RF systems is to specify
power in dBm, that is, decibels above 1 mW in 50 . Specifica-
tion of log amp input level in terms of power is strictly a conces-
sion to popular convention; they do not respond to power (tacitly
“power absorbed at the input”), but to the input voltage. The
use of dBV, defined as decibels with respect to a 1 V rms sine wave,
is more precise, although this is still not unambiguous because
waveform is also involved in the response of a log amp, which,
for a complex input (such as a CDMA signal) will not follow the
rms value exactly. Since most users specify RF signals in terms
of power—more specifically, in dBm/50 —we use both dBV
and dBm in specifying the performance of the AD8306, showing
equivalent dBm levels for the special case of a 50 environment.
Values in dBV are converted to dBm re 50 by adding 13.
Output Response Time and CF
The RSSI output has a low-pass corner frequency of 3.5 MHz,
which results in a 10% to 90% rise time of 73 ns. For low fre-
quency applications, the corner frequency can be reduced by
adding an external capacitor, CF, between FLTR (Pin 10) and
VLOG (Pin 16) as shown in Figure 24. For example, an exter-
nal 33 pF will reduce the corner frequency to 350 kHz, while
360 pF will set it to 35 kHz, in each case with an essentially
one-pole response.
Using the Limiter
Figure 27 shows the basic connections for operating the limiter
and the log output concurrently. The limiter output is a pair of
differential currents of magnitude, IOUT, from high impedance
(open-collector) sources. These are converted to equal-amplitude
voltages by supply-referenced load resistors, RLOAD. The limiter
output current is set by RLIM, the resistor connected between
Pin 9 (LMDR) and ground. The limiter output current is set
according the equation:
IOUT = –400 mV/RLIM
and has an absolute accuracy of ± 5%.
(5)
The supply referenced voltage on each of the limiter pins will
thus be given by:
VLIM = VS –400 mV × RLOAD/RLIM
(6)
–10–
REV. A

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