AD8330 Datasheet PDF - Analog Devices
| Part Number | AD8330 | |
| Description | Variable Gain Amplifier | |
| Manufacturers | Analog Devices | |
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Data Sheet
FEATURES
Fully differential signal path, also used with single-sided signals
Inputs from 0.3 mV to 1 V rms, rail-to-rail outputs
Differential RIN = 1 kΩ; ROUT (each output) 75 Ω
Automatic offset compensation (optional)
Linear-in-dB and linear-in-magnitude gain modes
0 dB to 50 dB, for 0 V < VDBS < 1.5 V (30 mV/dB)
Inverted gain mode: 50 dB to 0 dB at −30 mV/dB
×0.03 to ×10 nominal gain for 15 mV < VMAG < 5 V
Constant bandwidth: 150 MHz at all gains
Low noise: 5 nV/√Hz typical at maximum gain
Low distortion: ≤−62 dBc typical
Low power: 20 mA typical at VS of 2.7 V to 6 V
Available in a space-saving, 3 mm × 3 mm LFCSP package
APPLICATIONS
Pre-ADC signal conditioning
75 Ω cable driving adjust
AGC amplifiers
GENERAL DESCRIPTION
The AD8330 is a wideband variable gain amplifier for applications
requiring a fully differential signal path, low noise, well-defined
gain, and moderately low distortion, from dc to 150 MHz. The
input pins can also be driven from a single-ended source. The
peak differential input is ±2 V, allowing sine wave operation at
1 V rms with generous headroom. The output pins can drive
single-sided loads essentially rail-to-rail. The differential output
resistance is 150 Ω. The output swing is a linear function of the
voltage applied to the VMAG pin that internally defaults to 0.5 V,
providing a peak output of ±2 V. This can be raised to 10 V p-p,
limited by the supply voltage.
The basic gain function is linear-in-dB, controlled by the voltage
applied to Pin VDBS. The gain ranges from 0 dB to 50 dB for
control voltages between 0 V and 1.5 V—a slope of 30 mV/dB.
The gain linearity is typically within ±0.1 dB. By changing the
logic level on Pin MODE, the gain decreases over the same range,
with an opposite slope. A second gain control port is provided
at the VMAG pin and allows the user to vary the numeric gain
from a factor of 0.03 to 10. All the parameters of the AD8330
have low sensitivities to temperature and supply voltages. Using
VMAG, the basic 0 dB to 50 dB range can be repositioned to
any value from 20 dB higher (that is, 20 dB to 70 dB) to at least
Low Cost, DC to 150 MHz,
Variable Gain Amplifier
AD8330
FUNCTIONAL BLOCK DIAGRAM
ENBL
OFST CNTR
INHI
INLO
MODE
BIAS AND VREF
VGA CORE
GAIN INTERFACE
CM AND
OFFSET
CONTROL
OUTPUT
STAGES
OUTPUT
CONTROL
OPHI
OPLO
CMOP
VDBS CMGN COMM
Figure 1.
VMAG
30 dB lower (that is, –30 dB to +20 dB) to suit the application,
thereby providing an unprecedented gain range of over 100 dB.
A unique aspect of the AD8330 is that its bandwidth and pulse
response are essentially constant for all gains, over both the
basic 50 dB linear-in-dB range, but also when using the linear-
in-magnitude function. The exceptional stability of the HF
response over the gain range is of particular value in those VGA
applications where it is essential to maintain accurate gain law-
conformance at high frequencies.
An external capacitor at Pin OFST sets the high-pass corner of
an offset reduction loop, whose frequency can be as low as 5 Hz.
When this pin is grounded, the signal path becomes dc-coupled.
When used to drive an ADC, an external common-mode control
voltage at Pin CNTR can be driven to within 0.5 V of either ground
or VS to accommodate a wide variety of requirements. By default,
the two outputs are positioned at the midpoint of the supply, VS/2.
Other features, such as two levels of power-down (fully off and
a hibernate mode), further extend the practical value of this
exceptionally versatile VGA.
The AD8330 is available in 16-lead LFCSP and 16-lead QSOP
packages and is specified for operation from −40°C to +85°C.
Rev. H
Document Feedback
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responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2002–2016 Analog Devices, Inc. All rights reserved.
Technical Support
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AD8330
Data Sheet
Parameter
LINEAR GAIN INTERFACE
Peak Output Scaling, Gain vs. VMAG
Gain Multiplication Factor vs. VMAG
Usable Input Range
Default Voltage
Incremental Resistance
Bandwidth
CHIP ENABLE
Logic Voltage for Full Shutdown
Logic Voltage for Hibernate Mode
Logic Voltage for Full Operation
Current in Full Shutdown
Current in Hibernate Mode
Minimum Time Delay3
POWER SUPPLY
Supply Voltage
Quiescent Current
Test Conditions/Comments
Pin VMAG, Pin CMGN
See the Circuit Description section
Gain is nominal when VMAG = 0.5 V
VMAG O/C
For VMAG ≥ 0.1 V
Pin ENBL
Output pins remain at CNTR
VPSI, VPOS, VPSO, COMM, and CMOP pins
VDBS = 0.75 V
Min Typ
3.8 4.0
×2
0
0.48 0.5
4
150
1.3 1.5
2.3
20
1.5
1.7
2.7
20
Max Unit
4.2 V/V
5V
0.52 V
kΩ
MHz
0.5 V
1.7 V
V
100 µA
mA
µs
6V
27 mA
1 The use of an input common-mode voltage significantly different from the internally set value is not recommended due to its effect on noise performance. See Figure 56.
2 See the Typical Performance Characteristics section for more detailed information on distortion in a variety of operating conditions.
3 For minimum sized coupling capacitors.
Rev. H | Page 4 of 32
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