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PDF BD9406KS2 Data sheet ( Hoja de datos )
| Número de pieza | BD9406KS2 | |
| Descripción | 28bit Audio DSP | |
| Fabricantes | ROHM Semiconductor | |
| Logotipo |  |
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Digital Sound Processors for FPD TVs
28bit Audio DSP with Built-in
2ch ADC, 6ch DAC and ASRC
BD9406KS2
No.12083EAT01
●General Description
This LSI is the digital sound processor which made the use digital signal processing for FPD TVs.
DSP of ROHM original is used for the TV sound processor unit, and it excels in cost performance.
The asynchronous sampling rate converter is built in the digital input one line. The audio AD converter is built in
the analog input one line. The audio DA converters are built in the output three lines.
●Features
■ Digital Signal Processor unit
Word length:
28bit (Data RAM)
The fastest machine Cycle: 40.7ns (512fs, fs=48kHz)
Multiplier:
28x24 → 52 bit
Adder:
28+28 → 28bit
Data RAM:
256x28bit
Coefficient RAM:
128x24bit
Sampling Frequency:
fs=48kHz
Master Clock:
512fs (24.576Mhz, fs=48kHz)
■ Digital Signal Input (Stereo 4 lines): 16/20/24bit (I2S, Left-Justified, Right-Justified)
Digital Signal Output (Stereo 4 lines): 16/20/24bit (I2S, Left-Justified, Right-Justified, S/PDIF)
■ Asynchronous Sampling Rate Converter (Stereo 1 line): 32kHz/44.1kHz → 48kHz
■ Audio ADC: Stereo Input 1 line
20bit 64 x Over-sampling sigma delta ADC
S/N: 90dB
THD+N: 0.02% (Sine-wave 1kHz, -0.5dB)
Digital HPF (fc=1Hz)
■ Audio DAC: Stereo Output 2 lines
24bit 8x Over-sampling digital filter + 1bit sigma delta DAC
S/N: 96dB
THD+N: 0.005% (Sine-wave 1kHz, 0dB)
■ Audio 16bit DAC: Stereo Output 1 line
24bit 8x Over-sampling digital filter + Audio 16bit DAC
S/N: 90dB
THD+N: 0.03% (Sine-wave 1kHz, 0dB)
■ The sound signal processing function for FPD TVs
Pre-scaler, Channel Mixer, Pseudo Stereo, Surround, P2Bass, SAS,12-band parametric EQ, Master Volume,
L/R Balance, Compression, Post-scaler, Output Signal Clipper
(P2Bass and SAS are ROHM’s own sound effect functions.)
●Applications
Flat Panel TVs (LCD, Plasma)
www.rohm.com
© 2012 ROHM Co., Ltd. All rights reserved.
1/34
2012.03 - Rev.A
1 page  
BU9406KS2
Technical Note
●Pin Description(s)
No. Name
1 DGNDIO2
2 MODE
3 SCANTEST
Description of terminals
Digital I/O GND2
Test mode select pin
Digital test mode select pin
Type
－
A
A
4 SDA
I2C data I/O pin
D
5 SCL
6 I2CADR1
I2C transfer clock input pin
I2C slave address select pin 1
D
B
7 I2CADR2
I2C slave address select pin 2 B
8 RESETB
9 DVDDPLL
“L” -> Reset condition
PLL power supply
C
－
10 FILT1
11 DGNDPLL
PLL_ASRC filter connect G
terminal 1
PLL GND
－
12 FILT2
13 ANATEST
14 AVDDAD1
PLL_ASRC filter connect G
terminal 2
Analog test mode select pin
G
Audio ADC power supply 1
－
15 AGNDAD1
16 AINL
17 VREFAD
Audio ADC GND 1
Analog signal Lch input pin
ADC reference voltage pin
－
G
G
18 AINR
19 AGNDAD2
20 AVDDAD2
21 AGNDDA1
22 AOUTR1
23 AOUTL1
24 AVDDDA1
Analog signal Rch input pin
Audio ADC GND 2
Audio ADC power supply 2
Audio DAC GND 1
Audio DAC Rch output pin 1
Audio DAC Lch output pin 1
Audio DAC power supply 1
G
－
－
－
G
G
－
25 AVDDDAR2 Audio DAC Rch power supply 2 －
26 AOUTR2
Audio DAC Rch output pin 2
27 AGNDDAR2 Audio DAC Rch GND 2
G
－
28 VREFDA2 DAC reference voltage 2
29 AGNDDAL2 Audio DAC Lch GND 2
G
－
30 AOUTL2
Audio DAC Lch output pin 2
G
31 AVDDDAL2 Audio DAC Lch power supply 2 －
32 AVDDDAR3 Audio DAC Rch power supply 3 －
33 AOUTR3
Audio DAC Rch output pin3
G
34 AGNDDAR3 Audio DAC Rch GND 3
35 VREFDA3 DAC reference voltage 3
36 AGNDDAL3 Audio DAC Lch GND 3
－
G
－
37 AOUTL3
Audio DAC Lch output pin 3
G
38 AVDDDAL3 Audio DAC Lch power supply 3 －
39 ERROR
Sampling frequency input error D
pin
40 DVDDIO3 Digital I/O power supply 3
－
No. Name
41 DGNDIO3
42 DATAOC
43 BCKOC
44 LRCKOC
45 DATAOB
46 BCKOB
47 LRCKOB
48 DATAOA
49 BCKOA
50 DVDDCOR2
51 LRCKOA
52 DATAI1
53 BCKI1
54 LRCKI1
55 DATAI2
56 BCKI2
57 LRCKI2
58 DATAI3
59 DGNDIO1
60 XI
61 XO
62 DVDDIO1
63 BCKI3
64 LRCKI3
65 DATAI4
66 BCKI4
67 LRCKI4
68 AMCLKI1
69 AMCLKI2
70 DVDDCOR1
71 REG15
72 DVDDREG
73 LDOPOFF
74 DGNDREG
75 AMCLKI3
76 AMCLKI4S
77 AMCLKOA
78 AMCLKOB
79 AMCLKOC
80 DVDDIO2
Description of terminals
Type
Digital I/O GND 3
－
I2S audio data output C
D
I2S audio bit transfer clock output D
C
I2S audio LR sampling clock D
output C
I2S audio data output B
D
I2S audio bit transfer clock output D
B
I2S audio LR sampling clock D
output B
I2S audio data output A
D
I2S audio bit transfer clock output D
A
Connects with REG15 Pin
－
I2S audio LR sampling clock D
output A
I2S audio data input 1
E
I2S audio bit transfer clock input 1 E
I2S audio LR sampling clock input E
1
I2S audio data input 2
I2S audio bit transfer clock input 2
I2S audio LR sampling clock input
E
E
E
2
I2S audio data input 3
Digital I/O GND1
E
－
X’tal connecting (input) terminal F
X’tal connecting terminal
F
Digital I/O power supply 1
－
I2S audio bit transfer clock input 3 E
I2S audio LR sampling clock input E
3
I2S audio data input 4
I2S audio bit transfer clock input 4
I2S audio LR sampling clock input
E
E
E
4
I2S synchronous clock input 1
I2S synchronous clock input 2
E
E
Connects with REG15 Pin
－
Built in regulator voltage output G
Power supply for built in regulator －
Power off signal input for G
regulator
GND for built in regulator
－
I2S synchronous clock input 3
E
I2S synchronous clock Input 4 or E
S/PDIF output
I2S synchronous clock output A
I2S synchronous clock output B
D
D
I2S synchronous clock output C D
Digital I/O power supply 2
－
www.rohm.com
© 2012 ROHM Co., Ltd. All rights reserved.
5/34
2012.03 - Rev.A
5 Page 
BU9406KS2
Technical Note
2-3. DF2 Input Selection (SEL1, SEL2, SEL4)
Default = 0
Select Address
&h04 [ 6：4 ]
Value
0
1
2
3
4
Operation Description
Inputs analog signals converted to digital data
Inputs via S-P conversion 1 (refer to &h05[5:4])
Inputs via S-P conversion 2 (refer to &h05[1:0])
Inputs data before DSP processing
Inputs data after DSP processing
2-4. DF3 Input Selection (SEL1, SEL2, SEL5)
Default = 0
Select Address
&h04 [ 2：0 ]
Value
0
1
2
3
4
Operation Description
Inputs analog signals converted to digital data
Inputs via S-P conversion 1 (refer to &h05[5:4])
Inputs via S-P conversion 2 (refer to &h05[1:0])
Inputs data before DSP processing
Inputs data after DSP processing
2-5. S-P Conversion 1 Input Selection (SEL6）
Default = 0
Select Address
&h05 [ 5：4 ]
Value
0
1
2
3
Operation Description
Inputs data from I2S_IN1
Inputs data from I2S_IN2
Inputs data from I2S_IN3
Inputs data from I2S_IN4
2-6. S-P Conversion 2 Input Selection (SEL6)
Default = 0
Select Address
&h05 [ 1：0 ]
Value
0
1
2
3
Operation Description
Inputs data from I2S_IN1
Inputs data from I2S_IN2
Inputs data from I2S_IN3
Inputs data from I2S_IN4
2-7. Clock Output Selection (SEL&) to AMCLKOA Pin
Default = 0
Select Address
&h06 [ 6：4 ]
Value
0
1
2
3
4
5
Outputs Hi-z
Operation Description
Outputs 256fs (12.288MHz) clock used in DSP
Outputs clock from AMCLK_IN1
Outputs clock from AMCLK_IN2
Outputs clock from AMCLK_IN3
Outputs clock from AMCLK_IN4
www.rohm.com
© 2012 ROHM Co., Ltd. All rights reserved.
11/34
2012.03 - Rev.A
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet BD9406KS2.PDF ] | |
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