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BD9406KS2 PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 BD9406KS2
기능 28bit Audio DSP
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BD9406KS2 데이터시트, 핀배열, 회로
Digital Sound Processors for FPD TVs
28bit Audio DSP with Built-in
2ch ADC, 6ch DAC and ASRC
BD9406KS2
No.12083EAT01
General Description
This LSI is the digital sound processor which made the use digital signal processing for FPD TVs.
DSP of ROHM original is used for the TV sound processor unit, and it excels in cost performance.
The asynchronous sampling rate converter is built in the digital input one line. The audio AD converter is built in
the analog input one line. The audio DA converters are built in the output three lines.
Features
Digital Signal Processor unit
Word length:
28bit (Data RAM)
The fastest machine Cycle: 40.7ns (512fs, fs=48kHz)
Multiplier:
28x24 52 bit
Adder:
28+28 28bit
Data RAM:
256x28bit
Coefficient RAM:
128x24bit
Sampling Frequency:
fs=48kHz
Master Clock:
512fs (24.576Mhz, fs=48kHz)
Digital Signal Input (Stereo 4 lines): 16/20/24bit (I2S, Left-Justified, Right-Justified)
Digital Signal Output (Stereo 4 lines): 16/20/24bit (I2S, Left-Justified, Right-Justified, S/PDIF)
Asynchronous Sampling Rate Converter (Stereo 1 line): 32kHz/44.1kHz 48kHz
Audio ADC: Stereo Input 1 line
20bit 64 x Over-sampling sigma delta ADC
S/N: 90dB
THD+N: 0.02% (Sine-wave 1kHz, -0.5dB)
Digital HPF (fc=1Hz)
Audio DAC: Stereo Output 2 lines
24bit 8x Over-sampling digital filter + 1bit sigma delta DAC
S/N: 96dB
THD+N: 0.005% (Sine-wave 1kHz, 0dB)
Audio 16bit DAC: Stereo Output 1 line
24bit 8x Over-sampling digital filter + Audio 16bit DAC
S/N: 90dB
THD+N: 0.03% (Sine-wave 1kHz, 0dB)
The sound signal processing function for FPD TVs
Pre-scaler, Channel Mixer, Pseudo Stereo, Surround, P2Bass, SAS,12-band parametric EQ, Master Volume,
L/R Balance, Compression, Post-scaler, Output Signal Clipper
(P2Bass and SAS are ROHM’s own sound effect functions.)
Applications
Flat Panel TVs (LCD, Plasma)
www.rohm.com
© 2012 ROHM Co., Ltd. All rights reserved.
1/34
2012.03 - Rev.A




BD9406KS2 pdf, 반도체, 판매, 대치품
BU9406KS2
Block diagram
Technical Note
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
XO 61
DVDDIO1 62
BCKI3 63
LRCKI3 64
DATAI4 65
BCKI4 66
LRCKI4 67
AMCLKI1 68
AMCLKI2 69
DVDDCOR70
REG15 71
DVDDREG 72
LDOPOFF 73
DGNDREG 74
AMCLKI3 75
AMCLKI4S 76
AMCLKOA 77
AMCLKOB 78
AMCLKOC 79
DVDDIO2 80
Clock Gen.
Coef. RAM
Data RAM
I/F Logic
ASRC
LDO
15
DSP
DSP Program
Logic
(G/A)
x8 Over
Sampling
Digital Filter
x8 Over
Sampling
Digital Filter
x8 Over
Sampling
Digital Filter
Monitor
&
Command
I/F
I/F
Logic
PLL_ASRC
PLL_ASRC
Stereo
ADC
ΔΣ
Stereo
DAC
ΔΣ
Stereo
DAC
16bit
Stereo
DAC
40 DVDDIO3
39 ERROR
38 AVDDDAL3
37 AOUTL3
36 AGNDDAL3
35 VREFDA3
34 AGNDDAR3
33 AOUTR3
32 AVDDDAR3
31 AVDDDAL2
30 AOUTL2
29 AGNDDAL2
28 VREFDA2
27 AGNDDAR2
26 AOUTR2
25 AVDDDAR2
24 AVDDDA1
23 AOUTL1
22 AOUTR1
21 AGNDDA1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Fig.2 Block diagram
www.rohm.com
© 2012 ROHM Co., Ltd. All rights reserved.
4/34
2012.03 - Rev.A

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BD9406KS2 전자부품, 판매, 대치품
BU9406KS2
Technical Note
1. Command Interface
BU9406KS2 uses the I2C bus format for the command interface with the host CPU.
With BU9406KS2, in addition to write mode, read mode read-out is possible with many registers.
BU9406KS2 assigns a 1-byte select address in addition to the slave address and performs write-in and read-out.
The I2C bus slave mode format is as follows:
MSB
LSB MSB
LSB MSB
S Slave Address
A Select Address
A Data
LSB
AP
S: Start Condition
Slave Address:
Adds either a read mode (H”) or write mode (L”) bit to the slave address (7bit) configured by
I2CADR1 and I2CADR2, sending a total of 8 bits of data. (MSB first)
A: Acknowledge An acknowledge bit is added on to each bit of data transmitted.
When data transmission is being done correctly, “L” is transmitted.
“H” transmission means there was no acknowledge.
Select Address:
BU9406KS2 uses a 1-byte select address. (MSB first)
Data:
Data byte, transmitted data (MSB first)
P: Stop condition
SDA MSB 6
SCL
Start Condition
When SDA↓, SCL=”H”
5
LSB
Stop Condition
When SDA↑, SCL=”H”
1-1. Data Write-In
S Slave Address
MSB
A6 A5 A4
100
A Select Address
A Data
AP
: Master to Slave
: Slave to Master
Slave Address Configuration for BU9406KS2
LSB Pin Configuration Write Mode
A3 A2 A1 A0 R/W
I2CADR2 I2CADR1
Slave Address
00000
00
80h
01
82h
10
84h
11
86h
S Slave Address A Select Address
(Ex.)
80h
20h
A Data
A Data
00h 00h
: Master to Slave
A Data
00h
: Slave to Master
AP
www.rohm.com
© 2012 ROHM Co., Ltd. All rights reserved.
7/34
2012.03 - Rev.A

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BD9406KS2

28bit Audio DSP

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