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PDF PL138-48 Data sheet ( Hoja de datos )
| Número de pieza | PL138-48 | |
| Descripción | 1:4 Differential PECL Fanout Buffer | |
| Fabricantes | Microchip | |
| Logotipo |  |
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PL138-48
2.5V to 3.3V, Low-Skew, 1:4 Differential PECL Fanout Buffer
Features
• Four Differential 2.5V/3.3V LVPECL Output Pairs
• Output Frequency: ≤800 MHz
• Two Selectable Differential Input Pairs
• Translates Any Standard Single-Ended or
Differential Input Format to LVPECL Output. It
Can Accept the Following Standard Input Formats
and More:
- LVPECL, LVCMOS, LVDS, HCSL, SSTL,
LVHSTL, CML
• Output Skew: 25 ps (typ.)
• Part-to-Part Skew: 140 ps (typ.)
• Propagation Delay: 1.5 ns (typ.)
• Additive Jitter: <100 fs (max.)
• Operating Supply Voltage: 2.375V ~ 3.63V
• Operating Temperature Range from –40°C to
+85°C
• Package Availability: 16-Pin QFN and 20-Pin
TSSOP
General Description
The PL138-48 is a high performance low-cost 1:4
outputs differential LVPECL fanout buffer.
Microchip’s family of differential LVPECL buffers are
designed to operate from a single power supply of 2.5V
±5% or 3.3V ±10%. The differential input pairs are
designed to accept most standard input signal levels,
using an appropriate resistor bias network, and
produce a high quality set of outputs with the lowest
possible skew on the outputs, which is guaranteed for
part-to-part or lot-to-lot skew.
Designed to fit in a small form-factor package, the
PL138-48 offers up to 800 MHz of output operation with
very low-power consumption and lowest additive jitter
of any comparable device.
Block Diagram
2016 Microchip Technology Inc.
DS20005543B-page 1
1 page  
PL138-48
TEMPERATURE SPECIFICATIONS (Note 1)
Parameters
Sym. Min. Typ.
Max. Units
Conditions
Temperature Ranges
Ambient Operating Temperature
Junction Temperature
Storage Temperature Range
Soldering Temperature
TA –40 —
TJ — —
TS –65 —
———
+85
+110
+150
+260
°C Note 2
°C —
°C —
°C 10 sec.
Note 1:
The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable
junction temperature, and the thermal resistance from junction to air (i.e., TA, TJ, JA). Exceeding the
maximum allowable power dissipation will cause the device operating junction temperature to exceed the
maximum +125°C rating. Sustained junction temperatures above +125°C can impact the device reliability.
2: Operating temperature is guaranteed by design for all parts (commercial and industrial), but tested for
commercial grade only.
2016 Microchip Technology Inc.
DS20005543B-page 5
5 Page 
PL138-48
FIGURE 5-8:
CLK-IN Input Driven by a
Single-Ended LVPECL.
FIGURE 5-9:
HCSL Driver.
CLK-IN Input Driven by an
HCSL presents its signals very close to the ground rail,
below the VCMR range, so the HCSL signals cannot be
connected to the PL138 input directly. AC-coupling is
required for HCSL signals on the PL138 input.
TABLE 5-2:
INPUT CLOCK CONTROL
SELECTION
CLK_SEL
Selected Source
0 CLK-IN0
1 CLK-IN1
TABLE 5-3: INPUT CLOCK FUNCTION
Inputs
Outputs
CLK-EN CLKSEL Source Q0:Q3 Q0B:Q3B
0 0 CLK-IN0 Disabled Disabled
Low High
0 1 CLK-IN1 Disabled Disabled
Low High
1 0 CLK-IN0 Enabled Enabled
1 1 CLK-IN1 Enabled Enabled
5.2 Termination for LVPECL Outputs
The required termination for LVPECL is 50Ω to a
VCC-2V DC voltage level. Below are two schematics to
implement this termination.
FIGURE 5-10:
Input Logic Block Diagram.
TABLE 5-1:
INPUT PIN
CHARACTERISTICS
Input Parameter Min. Typ. Max. Units
CLK-IN0, Pull-Down —
CLK-IN1 Resistor
75
—
CLK-IN0B, Pull-Up & — 100 —
CLK_IN1B Pull-Down
Resistors
CLK-EN
Pull-Up
Resistor
— 50
—
CLKSEL Pull-Down —
Resistor
50
—
kΩ
FIGURE 5-11:
Schematic #1.
LVPECL Termination
• VCC = 3.3V
- Ideal values: R1 = 127Ω, R2 = 82.5Ω
- Commercial values (E24): R1 = 130Ω,
R2 = 82Ω
• VCC = 2.5V
- Ideal values: R1 = 250Ω, R2 = 62.5Ω
- Commercial values (E24): R1 = 240Ω,
R2 = 62Ω
2016 Microchip Technology Inc.
DS20005543B-page 11
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet PL138-48.PDF ] | |
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