|
|
PDF AD9683 Data sheet ( Hoja de datos )
| Número de pieza | AD9683 | |
| Descripción | Analog-to-Digital Converter | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de AD9683 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
Data Sheet
14-Bit, 170 MSPS/250 MSPS, JESD204B,
Analog-to-Digital Converter
AD9683
FEATURES
JESD204B Subclass 0 or Subclass 1 coded serial digital outputs
Signal-to-noise ratio (SNR) = 70.6 dBFS at 185 MHz AIN and
250 MSPS
Spurious-free dynamic range (SFDR) = 88 dBc at 185 MHz AIN
and 250 MSPS
Total power consumption: 434 mW at 250 MSPS
1.8 V supply voltages
Integer 1-to-8 input clock divider
Sample rates of up to 250 MSPS
Intermediate frequency (IF) sampling frequencies of up to
400 MHz
Internal analog-to-digital converter (ADC) voltage reference
Flexible analog input range
1.4 V p-p to 2.0 V p-p (1.75 V p-p nominal)
ADC clock duty cycle stabilizer (DCS)
Serial port control
Energy saving power-down modes
APPLICATIONS
Communications
Diversity radio systems
Multimode digital receivers (3G)
TD-SCDMA, WiMAX, W-CDMA, CDMA2000, GSM, EDGE, LTE
DOCSIS 3.0 CMTS upstream receive paths
HFC digital reverse path receivers
Smart antenna systems
Electronic test and measurement equipment
Radar receivers
COMSEC radio architectures
IED detection/jamming systems
General-purpose software radios
Broadband data applications
Ultrasound equipment
FUNCTIONAL BLOCK DIAGRAM
AVDD DRVDD DVDD AGND DGND DRGND
VIN+
VIN–
VCM
AD9683
PIPELINE
14-BIT ADC
JESD204B
INTERFACE
HIGH
SPEED
SERIALIZERS
CML, TX
OUTPUTS
SERDOUT0±
SYSREF±
SYNCINB±
CLK±
RFCLK
CONTROL
REGISTERS
CMOS
DIGITAL
INPUT
PDWN
CLOCK
GENERATION
CMOS DIGITAL FAST
INPUT/OUTPUT DETECT
CMOS
DIGITAL
OUTPUT
FD
RST SDIO SCLK CS
Figure 1.
GENERAL DESCRIPTION
The AD9683 is a 14-bit ADC with sampling speeds of up to
250 MSPS. The AD9683 supports communications applications
where low cost, small size, wide bandwidth, and versatility are
desired.
The ADC core features a multistage, differential pipelined
architecture with integrated output error correction logic. The
ADC core features wide bandwidth inputs supporting a variety
of user-selectable input ranges. An integrated voltage reference
eases design considerations. A duty cycle stabilizer (DCS) is
provided to compensate for variations in the ADC clock duty cycle,
allowing the converter to maintain excellent performance. The
JESD204B high speed serial interface reduces board routing
requirements and lowers pin count requirements for the
receiving device.
The ADC output data is routed directly to the JESD204B serial
output lane. These outputs are at CML voltage levels. Data can be
sent through the lane at the maximum sampling rate of 250 MSPS,
which results in a lane rate of 5 Gbps. Synchronization inputs
(SYNCINB± and SYSREF±) are provided.
Rev. D
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2013–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
AD9683
Data Sheet
SPECIFICATIONS
ADC DC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, DVDD = 1.8 V, maximum sample rate for speed grade, VIN = −1.0 dBFS differential input, 1.75 V p-p
full-scale input range, duty cycle stabilizer enabled, default SPI, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Gain Error
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)1
TEMPERATURE DRIFT
Offset Error
Gain Error
INPUT REFERRED NOISE
VREF = 1.75 V
ANALOG INPUT
Input Span
Input Capacitance2
Input Resistance3
Input Common-Mode Voltage
POWER SUPPLIES
Supply Voltage
AVDD
DRVDD
DVDD
Supply Current
IAVDD
IDRVDD + IDVDD
POWER CONSUMPTION
Sine Wave Input
Standby Power4
Power-Down Power5
Temperature
Full
Full
Full
Full
Full
25°C
Full
25°C
Full
Full
25°C
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Min
14
1.7
1.7
1.7
AD9683-170
Typ Max
Min
14
Guaranteed
±9
−6.6/−0.3
±0.8
±0.5
±1.6
±0.8
±7
±13
1.38
1.75
2.5
20
0.9
1.8 1.9
1.8 1.9
1.8 1.9
135 151
68 73
365 403
221
9
1.7
1.7
1.7
AD9683-250
Typ Max
Unit
Bits
Guaranteed
±9
−5.3/+1.2
±0.75
±0.5
±2.7
±1.5
mV
%FSR
LSB
LSB
LSB
LSB
±7 ppm/°C
±39 ppm/°C
1.42 LSB rms
1.75 V p-p
2.5 pF
20 kΩ
0.9 V
1.8 1.9
1.8 1.9
1.8 1.9
149 163
92 97
434 468
266
9
V
V
V
mA
mA
mW
mW
mW
1 Measured with a low input frequency, full-scale sine wave.
2 Input capacitance refers to the effective capacitance between one differential input pin and its complement.
3 Input resistance refers to the effective resistance between one differential input pin and its complement.
4 Standby power is measured with a low input frequency, full-scale sine wave, and the CLK± pins active. Address 0x08 is set to 0x20, and the PDWN pin is asserted.
5 Power-down power is measured with a low input frequency, a full-scale sine wave, RFCLK pulled high, and the CLK± pins active. Address 0x08 is set to 0x00, and the
PDWN pin is asserted.
Rev. D | Page 4 of 44
5 Page 
AD9683
ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter
Electrical
AVDD to AGND
DRVDD to DRGND
DVDD to DGND
VIN+, VIN− to AGND
CLK+, CLK− to AGND
RFCLK to AGND
VCM to AGND
CS, PDWN to DGND
SCLK to DGND
SDIO to DGND
RST to DGND
FD to DGND
SERDOUT0+, SERDOUT0− to AGND
SYNCINB+, SYNCINB− to DGND
SYSREF+, SYSREF− to AGND
Environmental
Operating Temperature Range
(Ambient)
Maximum Junction Temperature
Under Bias
Storage Temperature Range
(Ambient)
Rating
−0.3 V to +2.0 V
−0.3 V to +2.0 V
−0.3 V to +2.0 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to DVDD + 0.3 V
−0.3 V to DVDD + 0.3 V
−0.3 V to DVDD + 0.3 V
−0.3 V to DVDD + 0.3 V
−0.3 V to DVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DVDD + 0.3 V
−0.3 V to AVDD + 0.3 V
−40°C to +85°C
150°C
−65°C to +125°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Data Sheet
THERMAL CHARACTERISTICS
The exposed pad must be soldered to the ground plane of the
LFCSP. This increases the reliability of the solder joints,
maximizing the thermal capability of the package.
Table 7. Thermal Resistance
Package Type
Airflow
Velocity
(m/sec)
θJA1, 2
32-Lead LFCSP
5 mm × 5 mm
(CP-32-12)
0
1.0
2.5
37.1
32.4
29.1
θJC1, 3, 4
3.1
N/A
N/A
θJB1, 4, 5
20.7
N/A
N/A
Unit
°C/W
°C/W
°C/W
1 Per JEDEC 51-7, plus JEDEC 25-5 2S2P test board.
2 Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).
3 Per MIL-STD-883, Method 1012.1.
4 N/A = not applicable.
5 Per JEDEC JESD51-8 (still air).
Typical θJA is specified for a 4-layer printed circuit board (PCB)
with a solid ground plane. As shown in Table 7, airflow increases
heat dissipation, which reduces θJA. In addition, metal in direct
contact with the package leads from metal traces, through holes,
ground, and power planes reduces the θJA.
ESD CAUTION
Rev. D | Page 10 of 44
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9683.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| AD9680 | Dual Analog-to-Digital Converter | Analog Devices |
| AD9681 | 1.8 V Analog-to-Digital Converter | Analog Devices |
| AD9683 | Analog-to-Digital Converter | Analog Devices |
| AD9684 | Dual Analog-to-Digital Converter | Analog Devices |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |