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AD9879 데이터시트 PDF




Analog Devices에서 제조한 전자 부품 AD9879은 전자 산업 및 응용 분야에서
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부품번호 AD9879 기능
기능 Cable Modem
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AD9879 데이터시트, 핀배열, 회로
FEATURES
Low cost 3.3 V MxFE™ for
DOCSIS-, EURO-DOCSIS-, DVB-, DAVIC-compliant
set-top box and cable modem applications
232 MHz quadrature digital upconverter
12-bit direct IF DAC (TxDAC+™)
Up to 65 MHz carrier frequency DDS
Programmable sampling clock rates
16× upsampling interpolation LPF
Single-tone frequency synthesis
Analog Tx output level adjust
Direct cable amp interface
12-bit, 33 MSPS direct IF ADC
with optional video clamping input
10-bit, 33 MSPS direct IF ADC
Dual 7-bit, 16.5 MSPS sampling I/Q ADC
12-bit Σ-∆ auxiliary DAC
APPLICATIONS
Cable modem and satellite systems
Set-top boxes
Power line modem
PC multimedia
Digital communications
Data and video modems
QAM, OFDM, FSK modulation
GENERAL DESCRIPTION
The AD9879 is a single-supply set-top box and cable modem
mixed-signal front end. The device contains a transmit path
interpolation filter, complete quadrature digital upconverter,
and transmit DAC. The receive path contains a 12-bit ADC, a
10-bit ADC, and dual 7-bit ADCs. All internally required clocks
and an output system clock are generated by the phase-locked
loop (PLL) from a single crystal or clock input.
The transmit path interpolation filter provides an upsampling
factor of 16× with an output signal bandwidth as high as
8.3 MHz. Carrier frequencies up to 65 MHz with 26 bits of
frequency tuning resolution can be generated by the direct
digital synthesizer (DDS). The transmit DAC resolution is
12 bits and can run at sampling rates as high as 232 MSPS.
Analog output scaling from 0.0 dB to 7.5 dB in 0.5 dB steps is
available to preserve SNR when reduced output levels are
required.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
Mixed-Signal Front End
Set-Top Box, Cable Modem
AD9879
FUNCTIONAL BLOCK DIAGRAM
TX DATA
I
TX Q 16
12
SINC–1
DAC
TX
DDS
SPORT
4
CONTROL REGISTERS
Σ-
PLL
XM/N
Σ-_OUT
CA_PORT
MCLK
RXIQ[3:0]
MUX
8
ADC
MUX
2
2
RXI
RXQ
10
ADC
RXIF[11:0]
MUX
12
ADC
AD9879
MUX
CLAMP
Figure 1.
RX10
RX12
VIDEO
The 12-bit and 10-bit IF ADCs can convert direct IF inputs up
to 70 MHz and run at sample rates up to 33 MSPS. A video
input with an adjustable signal clamping level, along with the
10-bit ADC, allow the AD9879 to process an NTSC and a QAM
channel simultaneously.
The programmable Σ-Δ DAC can be used to control external
components, such as variable gain amplifiers (VGAs) or voltage
controlled tuners. The CA port provides an interface to the
AD8321/AD8323 or AD8322/AD8327 programmable gain
amplifier (PGA) cable drivers, enabling host processor control
via the MxFE SPORT.
The AD9879 is available in a 100-lead MQFP. It offers enhanced
receive path undersampling performance and lower cost when
compared with the pin-compatible AD9873. The AD9879 is
specified over the commercial (−40°C to +85°C) temperature
range.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.




AD9879 pdf, 반도체, 판매, 대치품
REVISION HISTORY
6/05—Rev. 0 to Rev. A
Updated Format.................................................................. Universal
Changed OSCOUT to REFCLK....................................... Universal
Changed REF CLK to REFCLK........................................ Universal
Changes to Specifications Section................................................... 4
Changes to Figure 13 ...................................................................... 21
Changes to Equation 18.................................................................. 24
Changes to Equation 21.................................................................. 24
Changes to Outline Dimensions ................................................... 30
Changes to Ordering Guide........................................................... 30
8/02—Revision 0: Initial Version
AD9879
Rev. A | Page 3 of 32

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AD9879 전자부품, 판매, 대치품
AD9879
Parameter
Signal-to-Noise Ratio (SNR)
Total Harmonic Distortion (THD)
Spurious-Free Dynamic Range (SFDR)
CHANNEL-TO-CHANNEL ISOLATION
Tx DAC-to-ADC Isolation (AOUT = 5 MHz)
Isolation Between Tx and IQ ADCs
Isolation Between Tx and 10-Bit ADC
Isolation Between Tx and 12-Bit ADC
ADC-to-ADC (AIN = –0.5 dBFS, f = 5 MHz)
Isolation Between IF10 and IF12 ADCs
Isolation Between Q and I Inputs
TIMING CHARACTERISTICS (10 pF Load)
Minimum RESET Pulse Width Low (tRL)
Digital Output Rise/Fall Time
Tx/Rx Interface
MCLK Frequency (fMCLK)
TxSYNC/TxIQ Setup Time (tSU)
TxSYNC/TxIQ Hold Time (tHD)
MCLK Rising Edge to
RxSYNC/RxIQ/IF Valid Delay (tMD)
REFCLK Rising or Falling Edge to
RxSYNC/RxIQ/IF Valid Delay (tOD)
REFCLK Edge to MCLK Falling Edge (tEE)
Serial Control Bus
Maximum SCLK Frequency (fSCLK)
Minimum Clock Pulse Width High (tPWH)
Minimum Clock Pulse Width Low (tPWL)
Maximum Clock Rise/Fall Time
Minimum Data/Chip-Select Setup Time (tDS)
Minimum Data Hold Time (tDH)
Maximum Data Valid Time (tDV)
CMOS LOGIC INPUTS
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Current
Logic 0 Current
Input Capacitance
CMOS LOGIC OUTPUTS (1 mA Load)
Logic 1 Voltage
Logic 0 Voltage
POWER SUPPLY
Supply Current, IS (Full Operation)
Analog Supply Current, IAS
Digital Supply Current, IDS
Supply Current, IS
Standby (PWRDN Pin Active)
Full Power-Down (Register 0x02 = 0xF9)
Power-Down Tx Path (Register 0x02 = 0x60)
Power-Down Rx Path (Register 0x02 = 0x19)
Temp
Full
Full
Full
Test Level
II
II
II
Min
46.2
44.9
25°C III
25°C III
25°C III
25°C III
25°C III
N/A N/A
Full II
Full II
Full II
Full II
Full II
Full II
Full II
Full II
Full II
Full II
Full II
Full II
Full II
Full II
25°C II
25°C II
25°C II
25°C II
25°C II
25°C II
25°C II
25°C II
25°C III
25°C III
25°C II
25°C III
25°C III
25°C III
5
2.8
3
3
0
TOSC/4 – 2.0
−1.0
30
30
25
0
VDRVDD – 0.7
VDRVDD – 0.6
1 IQ ADC in default mode. ADC Clock Select Register 8, Bit 3 set to 0.
Typ
57.2
−50.1
53.4
>60
>80
>80
>85
>50
3
163
95
68
119
16
113
110
Max
−44.5
Unit
Bits
dB
dB
4
66
1.0
TOSC/4 + 3.0
+1.0
15
1
30
0.4
12
12
0.4
184
126
dB
dB
dB
dB
dB
tMCLK cycles
ns
MHz
ns
ns
ns
ns
ns
MHz
ns
ns
ms
ns
ns
ns
V
V
µA
µA
pF
V
V
mA
mA
mA
mA
mA
mA
mA
Rev. A | Page 6 of 32

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