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PDF AD9266 Data sheet ( Hoja de datos )
| Número de pieza | AD9266 | |
| Descripción | 1.8V Analog-to-Digital Converter | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Data Sheet
16-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS,
1.8 V Analog-to-Digital Converter
AD9266
FEATURES
1.8 V analog supply operation
1.8 V to 3.3 V output supply
SNR
77.6 dBFS at 9.7 MHz input
71.1 dBFS at 200 MHz input
SFDR
93 dBc at 9.7 MHz input
80 dBc at 200 MHz input
Low power
56 mW at 20 MSPS
113 mW at 80 MSPS
Differential input with 700 MHz bandwidth
On-chip voltage reference and sample-and-hold circuit
2 V p-p differential analog input
DNL = −0.6/+1.1 LSB
Interleaved data output for reduced pin-count interface
Serial port control options
Offset binary, Gray code, or twos complement data format
Optional clock duty cycle stabilizer
Integer 1-to-8 input clock divider
Built-in selectable digital test pattern generation
Energy-saving power-down modes
Data clock output (DCO) with programmable clock and
data alignment
APPLICATIONS
Communications
Diversity radio systems
Multimode digital receivers
GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA
Smart antenna systems
Battery-powered instruments
Handheld scope meters
Portable medical imaging
Ultrasound
Radar/LIDAR
PET/SPECT imaging
FUNCTIONAL BLOCK DIAGRAM
AVDD
AGND
SDIO SCLK CSB DRVDD
RBIAS
VCM
VIN+
VIN–
VREF
SENSE
AD9266
SPI
ADC
CORE
PROGRAMMING DATA
OR
D15_D14
8
D1_D0
DCO
REF
SELECT
DIVIDE DUTY CYCLE
1 TO 8 STABILIZER
MODE
CONTROLS
CLK+ CLK–
Figure 1.
PDWN DFS MODE
PRODUCT HIGHLIGHTS
1. The AD9266 operates from a single 1.8 V analog power
supply and features a separate digital output driver supply
to accommodate 1.8 V to 3.3 V logic families.
2. The sample-and-hold circuit maintains excellent
performance for input frequencies up to 200 MHz and is
designed for low cost, low power, and ease of use.
3. A standard serial port interface supports various product
features and functions, such as data output formatting,
internal clock divider, power-down, DCO and data output
(D15_D14 to D1_D0) timing and offset adjustments, and
voltage reference modes.
4. The AD9266 is packaged in a 32-lead RoHS-compliant
LFCSP that is pin compatible with the AD9609 10-bit
ADC, the AD9629 12-bit ADC, and the AD9649 14-bit
ADC, enabling a simple migration path between 10-bit and
16-bit converters sampling from 20 MSPS to 80 MSPS.
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2010–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
AD9266
Data Sheet
SPECIFICATIONS
DC SPECIFICATIONS
AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty
cycle clock, DCS disabled, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Gain Error1
Differential Nonlinearity
(DNL)2
Integral Nonlinearity
(INL)2
TEMPERATURE DRIFT
Offset Error
INTERNAL VOLTAGE
REFERENCE
Output Voltage (1 V Mode)
Load Regulation Error
at 1.0 mA
INPUT-REFERRED NOISE
VREF = 1.0 V
ANALOG INPUT
Input Span, VREF = 1.0 V
Input Capacitance3
Input Common-Mode
Voltage
Input Common-Mode
Range
REFERENCE INPUT
RESISTANCE
POWER SUPPLIES
Supply Voltage
AVDD
DRVDD
Supply Current
IAVDD2
IDRVDD2 (1.8 V)
IDRVDD2 (3.3 V)
POWER CONSUMPTION
DC Input
Sine Wave Input2
(DRVDD = 1.8 V)
Sine Wave Input2
(DRVDD = 3.3 V)
Standby Power4
Power-Down Power
Temp
Full
AD9266-20/AD9266-40
Min Typ
Max
16
Full Guaranteed
Full
+0.05
±0.30
Full −2.5/−2.0
Full −0.9/+1.2
25°C −0.5/+0.6
Full ±5.5
25°C ±1.8
Full ±2
Full 0.983 0.995
Full 2
1.007
25°C
Full
Full
Full
Full
Full
0.5
2.8
2
6.5
0.9
7.5
1.3
Full 1.7 1.8
Full 1.7
1.9
3.6
Full 31.4/40.7 33.2/42.5
Full 1.7/3.3
Full 3.0/5.9
Full 57/73
Full
60/79
63/82
Full 66/93
Full 40
Full 0.5
AD9266-65
Min Typ
Max
16
Guaranteed
+0.05
±0.30
−1.0
−0.9/+1.7
−0.5/+1.0
±6.5
±2.4
±2
0.983 0.995
2
1.007
2.8
2
6.5
0.9
0.5
7.5
1.3
1.7 1.8
1.7
54.5
5.2
9.3
98
107
129
44
0.5
1.9
3.6
57.6
113
AD9266-80
Min Typ
Max
16
Guaranteed
+0.05
±0.30
+1.0
−0.9/+1.7
−0.6/+1.1
±6.2
±3.5
±2
0.983 0.995
2
1.007
2.8
2
6.5
0.9
0.5
7.5
1.3
1.7 1.8
1.7
62.5
6.3
11.6
113
124
151
44
0.5
1.9
3.6
65.7
130
Unit
Bits
% FSR
% FSR
LSB
LSB
LSB
LSB
ppm/°C
V
mV
LSB rms
V p-p
pF
V
V
kΩ
V
V
mA
mA
mA
mW
mW
mW
mW
mW
1 Measured with 1.0 V external reference.
2 Measured with a 10 MHz input frequency at rated sample rate, full-scale sine wave, with approximately 5 pF loading on each output bit.
3 Input capacitance refers to the effective capacitance between the differential inputs.
4 Standby power is measured with a dc input and the CLK active.
Rev. B | Page 4 of 32
5 Page 
AD9266
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Data Sheet
CLK+ 1
CLK– 2
AVDD 3
CSB 4
SCLK/DFS 5
SDIO/PDWN 6
DNC 7
DNC 8
AD9266
TOP VIEW
(Not to Scale)
24 AVDD
23 MODE/OR
22 DCO
21 (MSB) D15_D14
20 D13_D12
19 D11_D10
18 D9_D8
17 D7_D6
NOTES
1. DNC = DO NOT CONNECT.
2. THE EXPOSED PADDLE IS THE ONLY GROUND CONNECTION ON THE DEVICE. IT MUST
BE SOLDERED TO THE ANALOG GROUND OF THE PCB TO ENSURE PROPER FUNCTIONALITY,
HEAT DISSIPATION, NOISE, AND MECHANICAL STRENGTH.
Figure 3. Pin Configuration
Table 8. Pin Function Descriptions
Pin No.
Mnemonic
Description
0 EPAD
Exposed Paddle. The exposed paddle is the only ground connection on the device. It must be
soldered to the analog ground of the PCB to ensure proper functionality, heat dissipation, noise, and
mechanical strength.
1, 2 CLK+, CLK−
Differential Encode Clock for PECL, LVDS, or 1.8 V CMOS Inputs.
3, 24, 29, 32 AVDD
1.8 V Supply Pin for ADC Core Domain.
4 CSB
SPI Chip Select. Active low enable, 30 kΩ internal pull-up.
5 SCLK/DFS
SPI Clock Input in SPI Mode (SCLK). 30 kΩ internal pull-down.
Data Format Select in Non-SPI Mode (DFS). Static control of data output format. 30 kΩ internal pull-down.
DFS high = twos complement output; DFS low = offset binary output.
6
SDIO/PDWN
SPI Data Input/Output (SDIO). Bidirectional SPI data I/O with 30 kΩ internal pull-down.
Non-SPI Mode Power-Down (PDWN). Static control of chip power-down with 30 kΩ internal pull-
down. See Table 14 for details.
7 to 12
DNC
Do Not Connect.
14 to 21
D1_D0 (LSB) to
(MSB) D15_D14
ADC Digital Outputs.
13 DRVDD
1.8 V to 3.3 V Supply Pin for Output Driver Domain.
22 DCO
Data Clock Digital Output.
23 MODE/OR
Chip Mode Select Input (MODE)/Out-of-Range Digital Output in SPI Mode (OR).
Default = out-of-range (OR) digital output (SPI Register 0x2A, Bit 0 = 1).
Option = chip mode select input (SPI Register 0x2A, Bit 0 = 0).
Chip power-down (SPI Register 0x08, Bits[7:5] = 100b).
Chip standby (SPI Register 0x08, Bits[7:5] = 101b).
Normal operation, output disabled (SPI Register 0x08, Bits[7:5] = 110b).
Normal operation, output enabled (SPI Register 0x08, Bits[7:5] = 111b).
Out-of-range (OR) digital output only in non-SPI mode.
25 VREF
1.0 V Voltage Reference Input/Output. See Table 10.
26 SENSE
Reference Mode Selection. See Table 10.
27 VCM
Analog Output Voltage at Mid AVDD Supply. Sets common mode of the analog inputs.
28 RBIAS
Set Analog Current Bias. Connect to 10 kΩ (1% tolerance) resistor to ground.
30, 31
VIN−, VIN+
ADC Analog Inputs.
Rev. B | Page 10 of 32
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9266.PDF ] | |
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