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PDF AD9279 Data sheet ( Hoja de datos )
| Número de pieza | AD9279 | |
| Descripción | Octal LNA/VGA/AAF/ADC and CW I/Q Demodulator | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Octal LNA/VGA/AAF/ADC
and CW I/Q Demodulator
AD9279
FEATURES
8 channels of LNA, VGA, AAF, ADC, and I/Q demodulator
Low power: 141 mW per channel, TGC mode, 40 MSPS;
60 mW per channel, CW mode
10 mm × 10 mm, 144-ball CSP-BGA
TGC channel input-referred noise: 0.8 nV/√Hz, max gain
Flexible power-down modes
Fast recovery from low power standby mode: <2 μs
Overload recovery: <10 ns
Low noise preamplifier (LNA)
Input-referred noise: 0.75 nV/√Hz, gain = 21.3 dB
Programmable gain: 15.6 dB/17.9 dB/21.3 dB
0.1 dB compression: 1000 mV p-p/
750 mV p-p/450 mV p-p
Dual-mode active input impedance matching
Bandwidth (BW): >100 MHz
Variable gain amplifier (VGA)
Attenuator range: −45 dB to 0 dB
Postamp gain (PGA): 21 dB/24 dB/27 dB/30 dB
Linear-in-dB gain control
Antialiasing filter (AAF)
Programmable second-order LPF from 8 MHz to 18 MHz
Programmable HPF
Analog-to-digital converter (ADC)
SNR: 70 dB, 12 bits up to 80 MSPS
Serial LVDS (ANSI-644, low power/reduced signal)
CW mode I/Q demodulator
Individual programmable phase rotation
Output dynamic range per channel: >160 dBc/√Hz
Output-referred SNR: 155 dBc/√Hz, 1 kHz offset, −3 dBFS
GENERAL DESCRIPTION
The AD9279 is designed for low cost, low power, small size,
and ease of use for medical ultrasound and automotive radar. It
contains eight channels of a variable gain amplifier (VGA) with
a low noise preamplifier (LNA), an antialiasing filter (AAF), an
analog-to-digital converter (ADC), and an I/Q demodulator
with programmable phase rotation.
Each channel features a variable gain range of 45 dB, a fully
differential signal path, an active input preamplifier termination,
and a maximum gain of up to 52 dB. The channel is optimized
for high dynamic performance and low power in applications
where a small package size is critical.
The LNA has a single-ended-to-differential gain that is selectable
through the SPI. Assuming a 15 MHz noise bandwidth (NBW)
and a 21.3 dB LNA gain, the LNA input SNR is roughly 94 dB.
In CW Doppler mode, each LNA output drives an I/Q demod-
ulator that has independently programmable phase rotation
with 16 phase settings.
Power-down of individual channels is supported to increase
battery life for portable applications. Standby mode allows quick
power-up for power cycling. In CW Doppler operation, the
VGA, AAF, and ADC are powered down. The ADC contains
several features designed to maximize flexibility and minimize
system cost, such as a programmable clock, data alignment, and
programmable digital test pattern generation. The digital test
patterns include built-in fixed patterns, built-in pseudo random
patterns, and custom user-defined test patterns entered via the
serial port interface.
FUNCTIONAL BLOCK DIAGRAM
AVDD1 AVDD2
PDWN STBY
DRVDD
LO-A TO LO-H
LOSW-A TO LOSW-H
LI-A TO LI-H
LG-A TO LG-H
LNA
I/Q
DEMODULATOR
VGA
AAF
8 CHANNELS
12-BIT
ADC
SERIAL
LVDS
DOUTA+ TO DOUTH+
DOUTA– TO DOUTH–
LO
GENERATION
REFERENCE
SERIAL
PORT
INTERFACE
DATA
RATE
MULTIPLIER
FCO+
FCO–
DCO+
DCO–
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2010 Analog Devices, Inc. All rights reserved.
1 page  
AD9279
Parameter1
Input-Referred Noise Voltage
Noise Figure
Active Termination Matched
Unterminated
Correlated Noise Ratio
Output Offset
Signal-to-Noise Ratio (SNR)
Harmonic Distortion
Second Harmonic
Third Harmonic
Two-Tone Intermodulation (IMD3)
Channel-to-Channel Crosstalk
Channel-to-Channel Delay
Variation
GAIN ACCURACY
Gain Law Conformance Error
Linear Gain Error
Channel-to-Channel Matching
PGA Gain
GAIN CONTROL INTERFACE
Control Range
Gain Range
Scale Factor
Response Time
Gain+ Impedance
Gain− Impedance
CW DOPPLER MODE
LO Frequency
Phase Resolution
Output DC Bias (Single-Ended)
Output AC Current Range
Transconductance (Differential)
Test Conditions/Comments
GAIN+ = 1.6 V, RFB = ∞
LNA gain = 15.6 dB
LNA gain = 17.9 dB
LNA gain = 21.3 dB
GAIN+ = 1.6 V, RS = 50 Ω
LNA gain = 15.6 dB, RFB = 200 Ω
LNA gain = 17.9 dB, RFB = 250 Ω
LNA gain = 21.3 dB, RFB = 350 Ω
LNA gain = 15.6 dB, RFB = ∞
LNA gain = 17.9 dB, RFB = ∞
LNA gain = 21.3 dB, RFB = ∞
No signal, correlated/uncorrelated
fIN = 5 MHz at −10 dBFS, GAIN+ = 0 V,
fIN = 5 MHz at −1 dBFS, GAIN+ = 1.6 V
fIN = 5 MHz at −10 dBFS, GAIN+ = 0 V
fIN = 5 MHz at −1 dBFS, GAIN+ = 1.6 V
fIN = 5 MHz at −10 dBFS, GAIN+ = 0 V
fIN = 5 MHz at −1 dBFS, GAIN+ = 1.6 V
fRF1 = 5.015 MHz, fRF2 = 5.020 MHz,
ARF1 = 0 dB, ARF2 = −20 dB, GAIN+ =
1.6 VIMD3 relative to ARF2
fIN1 = 5.0 MHz at −1 dBFS
Overrange condition2
Full TGC path, fIN = 5 MHz, GAIN+ = 0 V to
1.6 V
25°C
0 < GAIN+ < 0.16 V
0.16 V < GAIN+ < 1.44 V
1.44 V < GAIN+ < 1.6 V
GAIN+ = 0.8 V, normalized for ideal AAF
loss
0.16 V < GAIN+ < 1.44 V
Differential
Single-ended
GAIN+ = 0 V to 1.6 V
45 dB change
Single-ended
Single-ended
fLO = f4LO/4
Per channel
CWI+, CWI−, CWQ+, CWQ−
Per CWI+, CWI−, CWQ+, CWQ−, each
channel enabled
Demodulated IOUT/VIN, per CWI+, CWI−,
CWQ+, CWQ−
LNA gain = 15.6 dB
LNA gain = 17.9 dB
LNA gain = 21.3 dB
Min
−35
−1.6
−1.6
−0.8
0
1
Rev. 0 | Page 4 of 44
Typ Max
1.12
0.96
0.81
5.6
4.5
3.3
3.5
2.9
2.3
−30
+35
67
59
−72
−72
−69
−59
−70
−60
−55
0.3
0.5
0.5
0.1
21/24/27/30
+1.6
+1.6
+0.8
1.6
45
28.0
750
10
70
10
22.5
1.5
±1.25
Unit
nV/√Hz
nV/√Hz
nV/√Hz
dB
dB
dB
dB
dB
dB
dB
LSB
dBFS
dBFS
dBc
dBc
dBc
dBc
dBc
dB
dB
Degrees
dB
dB
dB
dB
dB
dB
V
V
dB
dB/V
ns
MΩ
kΩ
MHz
Degrees
V
mA
1.8 mA/V
2.4 mA/V
3.5 mA/V
5 Page 
AD9279
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1 2 3 4 5 6 7 8 9 10 11 12
A LI-E LI-F LI-G LI-H VREF RBIAS GAIN+ GAIN– LI-A LI-B LI-C LI-D
B LG-E LG-F LG-G LG-H GND GND AVDD2 GND LG-A LG-B LG-C LG-D
C LO-E LO-F LO-G LO-H GND GND GND GND LO-A LO-B LO-C LO-D
D LOSW-E LOSW-F LOSW-G LOSW-H GND GND GND GND LOSW-A LOSW-B LOSW-C LOSW-D
E GND AVDD2 AVDD2 AVDD2 GND GND GND GND AVDD2 AVDD2 AVDD2 GND
F AVDD1 GND AVDD1 GND AVDD1 GND GND AVDD1 GND AVDD1 GND AVDD1
G GND AVDD1 GND AVDD1 GND GND GND GND AVDD1 GND AVDD1 GND
H CLK– GND GND GND GND GND GND GND GND GND GND CSB
J CLK+ GND CWQ+ GND CWI+ AVDD2 4LO+ GND GPO3 GPO1 PDWN SDIO
K GND GND CWQ– GND CWI– AVDD2 4LO– RESET GPO2 GPO0 STBY SCLK
L DRVDD DOUTH+ DOUTG+ DOUTF+ DOUTE+ DCO+ FCO+ DOUTD+ DOUTC+ DOUTB+ DOUTA+ DRVDD
M GND DOUTH– DOUTG– DOUTF– DOUTE– DCO– FCO– DOUTD– DOUTC– DOUTB– DOUTA– GND
Figure 4. Pin Configuration
2 4 6 8 10 12
1 3 5 7 9 11
A
B
C
D
E
F
G
H
J
K
L
M
TOP VIEW
(Not to Scale)
Figure 5.
Rev. 0 | Page 10 of 44
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9279.PDF ] | |
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