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54LS75 데이터시트 PDF




Motorola Semiconductors에서 제조한 전자 부품 54LS75은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


PDF 형식의 54LS75 자료 제공

부품번호 54LS75 기능
기능 4-BIT D LATCH
제조업체 Motorola Semiconductors
로고 Motorola Semiconductors 로고


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54LS75 데이터시트, 핀배열, 회로
4-BIT D LATCH
The TTL/MSI SN54 / 74LS75 and SN54 / 74LS77 are latches used as tem-
porary storage for binary information between processing units and input /out-
put or indicator units. Information present at a data (D) input is transferred to
the Q output when the Enable is HIGH and the Q output will follow the data
input as long as the Enable remains HIGH. When the Enable goes LOW, the
information (that was present at the data input at the time the transition oc-
curred) is retained at the Q output until the Enable is permitted to go HIGH.
The SN54 / 74LS75 features complementary Q and Q output from a 4-bit
latch and is available in the 16-pin packages. For higher component density
applications the SN54 / 74LS77 4-bit latch is available in the 14-pin package
with Q outputs omitted.
CONNECTION DIAGRAMS DIP (TOP VIEW)
Q0 Q1 Q1 E0–1 GND Q2 Q2 Q3
16 15 14 13 12 11 10 9
SN54 / 74LS75
1 2 3 4 56 78
Q0 D0 D1 E2–3 VCC D2 D3 Q3
Q0 Q1 E0–1 GND NC Q2 Q3
14 13 12 11 10 9 8
SN54 / 74LS77
1234567
D0 D1 E2–3 VCC D2 D3 NC
PIN NAMES
LOADING (Note a)
HIGH
LOW
D1–D4
E0–1
E2–3
Q1–Q4
Q1–Q4
Data Inputs
Enable Input Latches 0, 1
Enable Input Latches 2, 3
Latch Outputs (Note b)
Complimentary Latch Outputs (Note b)
0.5 U.L.
2.0 U.L.
2.0 U.L.
10 U.L.
10 U.L.
0.25 U.L.
1.0 U.L.
1.0 U.L.
5 (2.5) U.L.
5 (2.5) U.L.
NOTES:
a) 1 Unit Load (U.L.) = 40 µA HIGH.
b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
Temperature Ranges.
TRUTH TABLE
(Each latch)
tn tn + 1
DQ
HH
LL
NOTES:
tn = bit time before enable
negative-going transition
tn+1 = bit time after enable
negative-going transition
SN54/74LS75
SN54/74LS77
4-BIT D LATCH
LOW POWER SCHOTTKY
16
1
16
1
16
1
14
1
J SUFFIX
CERAMIC
CASE 620-09
N SUFFIX
PLASTIC
CASE 648-08
D SUFFIX
SOIC
CASE 751B-03
J SUFFIX
CERAMIC
CASE 632-08
14
1
14
1
N SUFFIX
PLASTIC
CASE 646-06
D SUFFIX
SOIC
CASE 751A-02
ORDERING INFORMATION
SN54LSXXJ
SN74LSXXN
SN74LSXXD
Ceramic
Plastic
SOIC
FAST AND LS TTL DATA
5-1




54LS75 pdf, 반도체, 판매, 대치품
SN54/74LS75 D SN54/74LS77
DATA
ENABLE
TO OTHER LATCH
LOGIC DIAGRAM
Q (SN54/74LS75 ONLY)
Q
GUARANTEED OPERATING RANGES
Symbol
Parameter
VCC
Supply Voltage
TA Operating Ambient Temperature Range
IOH Output Current — High
IOL Output Current — Low
AC SETUP REQUIREMENTS (TA = 25°C, VCC = 5.0 V)
Symbol
tW
ts
th
Parameter
Enable Pulse Width High
Setup Time
Hold Time
Min
20
20
0
54
74
54
74
54, 74
54
74
Min
4.5
4.75
– 55
0
Limits
Typ
Max
Unit
ns
ns
ns
Typ Max Unit
5.0 5.5
5.0 5.25
V
25 125 °C
25 70
– 0.4
mA
4.0 mA
8.0
Test Conditions
VCC = 5.0 V
AC WAVEFORMS
D 1.3 V
ts
1.3 V
th
E 1.3 V 1.3 V 1.3 V
tPLH
Q tPLH 1.3 V
Q tPHL 1.3 V
tPHL
tPHL
tPLH
1.3 V
1.3 V
tPHL tPLH
DEFINITION OF TERMS
SETUP TIME (ts) — is defined as the minimum time required for the correct logic level to be present at the logic input prior to the
clock transition from HIGH-to-LOW in order to be recognized and transferred to the outputs.
HOLD TIME (th) — is defined as the minimum time following the clock transition from HIGH-to-LOW that the logic level must be
maintained at the input in order to ensure continued recognition. A negative HOLD TIME indicates that the correct logic level may
be released prior to the clock transition from HIGH-to-LOW and still be recognized.
FAST AND LS TTL DATA
5-4

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