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기능 Data Retiming Phase-Locked Loop
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AD805 데이터시트, 핀배열, 회로
a
Data Retiming
Phase-Locked Loop
AD805*
FEATURES
CLOCK RECOVERY AND
155 Mbps Clock Recovery and Data Retiming
DATA RETIMING APPLICATION
Permits CCITT G.958 Type A Jitter Tolerance
Permits CCITT G.958 Type B Jitter Transfer
Random Jitter: 0.6؇ rms
Pattern Jitter: Virtually Eliminated
Jitter Peaking: Fundamentally None
DATA
INPUT
VOLTAGE
CONTROLLED
PHASE
SHIFTER
PHASE
DETECTOR
LOOP
FILTER
GAIN
Acquisition: 30 Bit Periods
Accepts NRZ Data without Preamble
Single Supply Operation: –5.2 V or +5 V
10 KH ECL Compatible
PRODUCT DESCRIPTION
The AD805 is a data retiming phase-locked loop designed for
Ouse with a Voltage-Controlled Crystal Oscillator (VCXO) to
perform clock recovery and data retiming on Nonreturn to Zero
B(NRZ) data. The circuit provides clock recovery and data
Sretiming on standard telecommunications STS-3 or STM-1
data (155.52 Mbps). A Vectron C0-434Y Series VCXO circuit
Ois used with the AD805 for specification purposes. Similar
circuit performance can be obtained using other commercially
Lavailable VCXO circuits. The AD805-VCXO circuit used for
Eclock recovery and data retiming can also be used for large
factor frequency multiplication.
TEThe AD805-VCXO circuit meets or exceeds CCITT G.958
RETIMING
MODULE
VCXO
(EXTERNAL)
AD805
RECOVERED
CLOCK
RETIMED
DATA
phase shifter, phase detector, and loop filter, act to align input
data phase errors to the stable recovered clock provided by the
VCXO. The range of the voltage-controlled phase shifter, at
least 2 Unit Intervals (UI), and the bandwidth of this loop, at
roughly 3 MHz, provide the circuit with its wideband jitter
tolerance characteristic.
The circuit can acquire lock to input data very quickly, within
44 bit periods, due to the accuracy of the VCXO and the action
of the data retiming loop. Typical integrated second-order PLLs
take at least several thousand bit periods to acquire lock. This is
due to their having a wide tuning range VCO. Decreasing the
regenerator specifications for STM-I Type A jitter tolerance and loop damping of a traditional second-order PLL shortens the
STM-1 Type B jitter transfer. The simultaneous Type A, wide- length of the circuit’s acquisition time, but at the expense of
band jitter tolerance and Type B, narrow-band jitter transfer
greater jitter peaking.
allows the use of the AD805-VCXO circuit in a regenerative
application to overcome optical line system interworking limit-
ations based on signal retiming using Type A passive tuned
device technology such as Surface-Acoustic-Wave (SAW) or
dielectric resonator filters, with Type B active devices such as
Phase-Locked Loops (PLLs).
The AD805-VCXO circuit is a second- order PLL that has no
jitter peaking. The zero used to stabilize the control loop of the
traditional second-order PLL effects the closed-loop transfer
function, causing jitter peaking in the jitter transfer function. In
the AD805-VCXO circuit, the zero needed to stabilize the loop
is implemented in the feedback path, in the voltage-controlled
The circuit VCXO provides a stable and accurate clock fre-
phase shifter. Placing the zero in the feedback path results in
quency signal with or without input data. The AD805 works
fundamentally no jitter peaking since the zero is absent from the
with the VCXO to dynamically adjust the recovered clock fre-
closed-loop transfer function.
quency to the frequency associated with the input data. This
frequency control loop tracks any low frequency component of
jitter on the input data. Since the circuit uses the VCXO for
clock recovery, it has a high Q for excellent wideband jitter at-
tenuation. The jitter transfer characteristic of the circuit is with-
in the jitter transfer requirements for a CCITT G.958 STM-1
Type B regenerator, which has a corner frequency of 30 kHz.
The AD805 overcomes the higher frequency jitter tolerance
limitations associated with traditional high Q, PLL based clock
and data recovery circuits through the use of its data retiming
loop. This loop, made up of the AD805’s voltage-controlled
*Protected by U.S. Patent No. 5,036,298
Output jitter, determined primarily by the VCXO, is a very low
0.6° rms. Jitter due to variations in input data density, pattern
jitter, is virtually eliminated in the circuit due to the AD805’s
patented phase detector.
The data retiming loop of the AD805 can be used with a passive
tuned circuit (155.52 MHz) such as a bandpass or a SAW filter
for clock recovery and data retiming. The data retiming loop
acts to servo the phase of the input data to the phase of the
recovered clock from the passive tuned circuit in this type of
application (see APPLICATIONS).
The AD805 uses 10 KH ECL levels and consumes 375 mW
from a +5 V or a –5.2 V supply. The device is specified for
REV. 0
operation over the industrial temperature range of –40°C to
+85°C and is available in a 20-pin plastic DIP.
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 World Wide Web Site: http://www.analog.com
Fax: 617/326-8703
© Analog Devices, Inc., 1996




AD805 pdf, 반도체, 판매, 대치품
AD805
GLOSSARY
Jitter Tolerance
AD805 performance is specified using a Vectron C0-434Y ECL Jitter tolerance is a measure of the circuit’s ability to track a
Series Hybrid VCXO, SCD No. 434Y2365.
jittery input data signal. Jitter on the input data is best thought
Nominal Data Rate
This is the data rate that the circuit is specified to operate on.
The data format is Nonreturn to Zero (NRZ).
Operating Temperature Range (TMIN to TMAX)
This is the operating temperature range of the AD805 in the
circuit. Each of the additional components of the circuit is held
of as phase modulation and is usually specified in Unit Intervals
(UI). The circuit will have a bit error rate less than 1 × 10–10
when in lock and retiming input data that has the specified jitter
applied to it.
Refer to the THEORY OF OPERATION section for a descrip-
tion of the jitter tolerance of the AD805-VCXO circuit.
at 25°C, nominal. The operating temperature range of the
Jitter Transfer
circuit can be extended to the operating temperature range of
The circuit exhibits a low-pass filter response to jitter applied to
the AD805 through the selection of circuit components that
its input data. The circuit jitter transfer characteristics are
operate from TMIN to TMAX.
Tracking Range
This is the range of input data rates over which the circuit will
remain in lock. The VCXO CONTROL voltage range and the
VCXO frequency range determine circuit tracking range.
Capture Range
OThis is the range of frequencies over which the circuit can
acquire lock. The VCXO CONTROL voltage range and the
BVCXO frequency range determine circuit capture range.
SStatic Phase Error
This is the steady-state phase difference, in degrees, between the
Orecovered clock sampling edge and the optimum sampling
instant, which is assumed to be halfway between the rising and
Lfalling edges of a data bit. Gate delays between the signals that
Edefine static phase error and IC input and output signals
prohibit direct measurement of static phase error.
TERecovered Clock Skew, TRCS
measured using the method described in CCITT Recommenda-
tion G.958, Geneva 1990, Section 6.3.2. This method involves
applying sinusoidal input jitter up to the jitter tolerance mask
level for an STM-1 Type A regenerator.
Bandwidth
This describes the frequency at which the circuit attenuates
sinusoidal input jitter by 3 dB.
Peaking
This describes the maximum jitter gain of the circuit in dB.
Acquisition Time
This is the transient time, measured in bit periods, required for
the circuit to lock on input data from its free-running state.
Buffered Clock Distortion
This is a measure of the duty cycle distortion at the AD805
CLKOUT signals relative to the duty cycle distortion at the
AD805 CLKIN signals.
Bit Error Rate vs. Signal-to-Noise Ratio
This is the time difference, in ns, between the recovered clock
The AD805 is intended to operate with standard ECL signal
signal rising edge midpoint and midpoint of the rising or falling levels at the data input. Although not recommended, smaller
edge of the output data signal. Refer to Figure 1.
input signals are tolerable. Figure 6 shows the bit error rate
Data Transition Density,
performance versus input signal-to-noise ratio for input signal
This is a measure of the number of data transitions, from “0” to amplitudes of full 900 mV ECL, and decreased amplitudes of
“1” and from “1” to “0,” over many clock periods. ρ is the ratio 80 mV and 20 mV. Wideband amplitude noise is summed with
(0 ≤ ρ ≤ 1) of data transitions to clock periods.
the data signals as shown in Figure 2. The full ECL, 80 mV,
Transitionless Data Run
and 20 mV input signals give virtually indistinguishable results.
This is measured by interrupting an input data pattern with
The axes used for Figure 6 are scaled so that the theoretical Bit
ρ = 1/2 with a block of data bits without transitions, and then
Error Rate vs. Signal to Noise Ratio curve appears as a straight
reapplying the ρ = 1/2 input data. The circuit will handle this
line. The curve that fits the actual data points has a slope that
sequence without making a bit error. The length of the block of matches the slope of the theoretical curve for all but the higher
input data without transitions that an AD805-VCXO circuit can values of signal-to-noise ratio and lower values of bit error rate.
handle is a function of the VCXO K0. The VCXO in the circuit
of Figure 12 has a K0 of 60 radians/volt, nominally.
Jitter
This is the dynamic displacement of digital signals from their
long term average positions, measured in degrees rms, or Unit
For high values of signal-to-noise ratio, the noise generator used
clips, and therefore is not true Gaussian. The extreme peaks of
the noise cause bit errors for high signal to noise ratios and low
bit error rates. The clipping of the noise waveform limits bit
errors in these cases.
Intervals (UI). Jitter on the input data can cause dynamic phase
errors on the recovered clock. Jitter on the recovered clock
causes jitter on the retimed data.
Output Jitter
This is the jitter on the retimed data, in degrees rms, due to a
specific pattern or some pseudo-random input data sequence
(PRN Sequence). The random output jitter of the VCXO
contributes to Output Jitter.
–4– REV. 0

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AD805 전자부품, 판매, 대치품
AD805
The gain of the loop integrator is small for high jitter frequen-
APPLICATIONS
cies, so that larger phase differences between the phase detector 155.52 MBPS CLOCK RECOVERY AND DATA RETIMING
inputs are needed to make the internal loop control voltage big USING AT&T 157-TYPE VHF VOLTAGE-CONTROLLED
enough to tune the range of the VCPS. Large phase errors at
CRYSTAL OSCILLATOR
high jitter frequencies cannot be tolerated. In this region, the
The AD805 design can be used with any VCXO circuit that has
gain of the loop integrator determines the jitter accommodation. a gain of roughly 1 ϫ 106 rad/volt-sec, a frequency pull range of
Since the gain of the loop integrator declines linearly with
at least ± 50 ppm, a positive slope (a greater VCXO control
frequency, jitter accommodation decreases with increasing jitter voltage corresponds to a greater output frequency) and a
frequency. At the highest frequencies, the loop gain is very small modulation bandwidth of 500 kHz. These VCXO parameters
and little tuning of the VCPS can be expected. In this case, jitter contribute to overall circuit low frequency jitter tolerance and
accommodation is determined by the eye opening of the input
jitter transfer.
data, the static phase error and the residual loop jitter. The jitter The output jitter of the overall circuit is largely determined by
accommodation is roughly 0.5 UI in this region. The corner
the output jitter of the VCXO. The AD805 adds little jitter
frequency between the declining slope and the flat region is the
3 MHz closed-loop bandwidth of the AD805’s internal
delay-locked loop.
USING THE AD805
Ground Planes
OUse of two ground planes, an analog ground plane and a digital
ground plane, is recommended. This will isolate noise that may
Bbe on the digital ground plane from the analog ground plane.
Power Supply Connections
SPower supply decoupling should take place as close to the IC as
Opossible. This will keep noise that may be on a power supply
from affecting circuit performance.
LUse of a 10 µF tantalum capacitor between VEE and ground is
Erecommended.
TUse of 0.1 µF ceramic capacitors between IC power supply or
Esubstrate pins and either analog or digital ground is recom-
since it just buffers the VCXO frequency output, adding
distortion (duty cycle distortion) of only ± 0.5%.
Overall circuit jitter bandwidth is determined by the slope of the
VCXO output frequency vs. control voltage curve. A greater
slope corresponds to a greater jitter bandwidth.
Figure 12 shows a schematic of the AD805 in a 155.52 Mbps
clock recovery and data retiming application with an AT&T
157-Type VCXO (see insert). Figures 15 and 16 show typical
jitter tolerance and jitter transfer curves for the circuit.
Note that the 157-Type VCXO control voltage bandwidth
(modulation bandwidth) varies with respect to control voltage
from 80 kHz to 500 kHz. The low value of this modulation
bandwidth causes some jitter peaking when used with the
AD805. The limited modulation bandwidth introduces excess
phase in the frequency control loop through the VCXO. This
causes the frequency control loop to become less damped. Jitter
peaking of 1 dB or 2 dB results in the jitter transfer function.
mended. Refer to schematic, Figure 12, for advised connections. The compensation network on the VCXO control voltage
The ceramic capacitors should be placed as close to the IC pins between the AD805 and the 157-Type VCXO shown in Figure
as possible.
12, effectively reduces the high frequency loop gain through the
Connections from VEE to load resistors for DATAIN, DATAOUT, frequency control loop. The addition of this compensation
CLKIN, and CLKOUT signals should be individual, not daisy network eliminates jitter peaking. The compensation network
chained. This will avoid crosstalk on these signals.
1 kresistor works with the AD805 VCXO CONTROL 1 k
Transmission Lines
Use of 50 transmission lines are recommended for DATAIN,
DATAOUT, CLKIN, and CLKOUT signals.
output impedance to halve the loop crossover frequency. This
avoids excess phase caused by the limited modulation band-
width of the 157-Type VCXO.
Terminations
Termination resistors should be used for DATAIN, CLKIN,
DATAOUT, and CLKOUT signals. Metal, thick film, 1%
tolerance resistors are recommended. Termination resistors for
the DATAIN and CLKIN signals should be placed as close as
possible to the DATAIN and CLKIN pins.
Input Buffer
Use of an input buffer, such as a 10H116 Line Receiver IC, is
suggested for an application where the DATAIN signals do not
come directly from an ECL gate, or where noise immunity on
the DATAIN signals is an issue.
REV. 0
–7–

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