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AD7910 데이터시트 PDF




Analog Devices에서 제조한 전자 부품 AD7910은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

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부품번호 AD7910 기능
기능 10-/12-Bit ADCs
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AD7910 데이터시트, 핀배열, 회로
250 kSPS,
10-/12-Bit ADCs in 6-Lead SC70
AD7910/AD7920
FEATURES
Throughput rate: 250 kSPS
Specified for VDD of 2.35 V to 5.25 V
Low power
3.6 mW typ at 250 kSPS with 3 V supplies
12.5 mW typ at 250 kSPS with 5 V supplies
Wide input bandwidth
71 dB SNR at 100 kHz input frequency
Flexible power/serial clock speed management
No pipeline delays
High speed serial interface
SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible
Standby mode: 1 μA max
6-lead SC70 package
8-lead MSOP package
APPLICATIONS
Battery-powered systems
Personal digital assistants
Medical instruments
Mobile communications
Instrumentation and control systems
Data acquisition systems
High speed modems
Optical sensors
GENERAL DESCRIPTION
The AD7910/AD79201 are, respectively, 10-bit and 12-bit, high
speed, low power, successive approximation ADCs. The parts
operate from a single 2.35 V to 5.25 V power supply and feature
throughput rates up to 250 kSPS. The parts contain a low noise,
wide bandwidth track-and-hold amplifier that can handle input
frequencies in excess of 13 MHz.
The conversion process and data acquisition are controlled
using CS and the serial clock, allowing the devices to interface
with microprocessors or DSPs. The input signal is sampled on
the falling edge of CS and the conversion is initiated at this
point. There are no pipeline delays associated with the part.
The AD7910/AD7920 use advanced design techniques to
achieve very low power dissipation at high throughput rates.
The reference for the part is taken internally from VDD. This
allows the widest dynamic input range to the ADC. Thus, the
analog input range for the part is 0 to VDD. The conversion rate
is determined by the SCLK.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
FUNCTIONAL BLOCK DIAGRAM
VDD
VIN T/H
10-/12-BIT
SUCCESSIVE
APPROXIMATION
ADC
CONTROL LOGIC
AD7910/AD7920
GND
Figure 1.
SCLK
SDATA
CS
PRODUCT HIGHLIGHTS
1. 10-/12-bit ADCs in SC70 and MSOP packages.
2. Low power consumption.
3. Flexible power/serial clock speed management. The
conversion rate is determined by the serial clock, allowing
the conversion time to be reduced through the serial clock
speed increase. This allows the average power consumption
to be reduced when power-down mode is used while not
converting. The part also features a power-down mode to
maximize power efficiency at lower throughput rates.
Current consumption is 1 μA maximum and 50 nA typically
when in power-down mode.
4. Reference derived from the power supply.
5. No pipeline delay. The parts feature a standard successive
approximation ADC with accurate control of the sampling
instant via a CS input and once-off conversion control.
1 Protected by U.S. Patent No. 6,681,332.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
© 2005 Analog Devices, Inc. All rights reserved.




AD7910 pdf, 반도체, 판매, 대치품
AD7910/AD7920
Parameter1
Power Dissipation6
Normal Mode (Operational)
Full Power-Down
A Grade1, 2
15
4.2
5
3
1 Temperature range from −40°C to +85°C.
2 Operational from VDD = 2.0 V, with input high voltage (VINH) 1.8 V min.
3 See the Terminology section.
4 SC70 values guaranteed by characterization.
5 Guaranteed by characterization.
6 See the Power vs. Throughput Rate section.
Unit
mW max
mW max
μW max
μW max
Test Conditions/Comments
VDD = 5 V, fSAMPLE = 250 kSPS
VDD = 3 V, fSAMPLE = 250 kSPS
VDD = 5 V
VDD = 3 V
AD7920
VDD = 2.35 V to 5.25 V, fSCLK = 5 MHz, fSAMPLE = 250 kSPS, TA = TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter1
DYNAMIC PERFORMANCE
Signal-to-Noise + Distortion (SINAD)3
Signal-to-Noise Ratio (SNR)3
Total Harmonic Distortion (THD)3
Peak Harmonic or Spurious Noise (SFDR)3
Intermodulation Distortion (IMD)3
Second-Order Terms
Third-Order Terms
Aperture Delay
Aperture Jitter
Full Power Bandwidth
DC ACCURACY
Resolution
Integral Nonlinearity3
Differential Nonlinearity
Offset Error3, 5
Gain Error3, 5
Total Unadjusted Error (TUE)3, 5
ANALOG INPUT
Input Voltage Ranges
DC Leakage Current
Input Capacitance
A Grade 1, 2
70
69
71.5
69
68
71
70
70
69
−80
−82
−84
−84
10
30
13.5
2
12
± 0.75
±0.75
±1.5
±1.5
0 to VDD
±0.5
20
B Grade1, 2
70
69
71.5
69
68
71
70
70
69
−80
−82
−84
−84
10
30
13.5
2
12
±1.5
−0.9/+1.5
±1.5
±0.2
±1.5
±0.5
±2
0 to VDD
±0.5
20
Unit
dB min
dB min
dB typ
dB min
dB min
dB min
dB min
dB min
dB min
dB typ
dB typ
dB typ
dB typ
ns typ
ps typ
MHz typ
MHz typ
Bits
LSB max
LSB typ
LSB max
LSB typ
LSB max
LSB typ
LSB max
LSB typ
LSB max
V
μA max
pF typ
Test Conditions/Comments
fIN = 100 kHz sine wave
VDD = 2.35 V to 3.6 V, TA = 25°C
VDD = 2.4 V to 3.6 V
VDD = 2.35 V to 3.6 V
VDD = 4.75 V to 5.25 V, TA = 25°C
VDD = 4.75 V to 5.25 V
VDD = 2.35 V to 3.6 V, TA = 25°C
VDD = 2.4 V to 3.6 V
VDD = 4.75 V to 5.25 V, TA = 25°C
VDD = 4.75 V to 5.25 V
fa = 100.73 kHz, fb = 90.72 kHz
fa = 100.73 kHz, fb = 90.72 kHz
@ 3 dB
@ 0.1 dB
B Grade4
Guaranteed no missed codes to 12 bits
Track-and-hold in track, 6 pF typ when in hold
Rev. C | Page 4 of 24

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AD7910 전자부품, 판매, 대치품
TIMING EXAMPLES
Figure 3 and Figure 4 show some of the timing parameters from
Table 3.
TIMING EXAMPLE 1
From Figure 4, having fSCLK = 5 MHz and a throughput rate of
250 kSPS gives a cycle time of t2 + 12.5(1/fSCLK) + tACQ = 4 μs.
With t2 = 10 ns min, this leaves tACQ to be 1.49 μs. This 1.49 μs
satisfies the requirement of 250 ns for tACQ. From Figure 4, tACQ
comprises 2.5(1/fSCLK) + t8 + tQUIET, where t8 = 36 ns max. This
allows a value of 954 ns for tQUIET, satisfying the minimum
requirement of 50 ns.
AD7910/AD7920
TIMING EXAMPLE 2
The AD7920 can also operate with slower clock frequencies.
From Figure 4, having fSCLK = 3.4 MHz and a throughput rate of
150 kSPS gives a cycle time of t2 + 12.5(1/fSCLK) + tACQ = 6.66 μs.
With t2 = 10 ns min, this leaves tACQ to be 2.97 μs. This 2.97 μs
satisfies the requirement of 250 ns for tACQ. From Figure 4, tACQ
comprises 2.5(1/fSCLK) + t8 + tQUIET, t8 = 36 ns max. This allows a
value of 2.19 μs for tQUIET, satisfying the minimum requirement
of 50 ns. As in this example and with other slower clock values,
the signal may already be acquired before the conversion is
complete, but it is still necessary to leave 50 ns minimum tQUIET
between conversions. In this example, the signal should be fully
acquired at approximately Point C in Figure 4.
CS
SCLK
tCONVERT
t2 t6
12345
SDATA
THREE-
STATE
t3
Z ZERO
ZERO
t4
ZERO
4 LEADING ZEROS
DB11
t7
DB10
B
13
14
t5
15 16
t8
DB2
DB1
DB0
Figure 3. AD7920 Serial Interface Timing Diagram
t1
tQUIET
THREE-STATE
CS
SCLK
tCONVERT
t2
1 2 345
12.5(1/fSCLK)
B
13
C
14
15
t8
16
tACQ
1/THROUGHPUT
Figure 4. Serial Interface Timing Example
tQUIET
Rev. C | Page 7 of 24

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