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기능 RF Digital-to-Analog Converters
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AD9162 데이터시트, 핀배열, 회로
Data Sheet
11-Bit/16-Bit, 12 GSPS,
RF Digital-to-Analog Converters
AD9161/AD9162
FEATURES
DAC update rate up to 12 GSPS (minimum)
Direct RF synthesis at 6 GSPS (minimum)
DC to 2.5 GHz in baseband 1× bypass mode
DC to 6 GHz in 2× nonreturn-to-zero (NRZ) mode
1.5 GHz to 7.5 GHz in Mix-Mode
Bypassable interpolation (1× or bypass mode)
2×, 3×, 4×, 6×, 8×, 12×, 16×, 24×
Excellent dynamic performance
APPLICATIONS
Broadband communications systems
DOCSIS 3.1 cable modem termination system (CMTS)/
video on demand (VOD)/edge quadrature amplitude
modulation (EQAM)
Wireless communications infrastructure
W-CDMA, LTE, LTE-A, point to point
Instrumentation, automatic test equipment (ATE)
Radars and jammers
GENERAL DESCRIPTION
In baseband mode, wide bandwidth capability combines with
high dynamic range to support DOCSIS 3.1 cable infrastructure
compliance from the minimum of two carriers to full maximum
spectrum of 1.794 GHz. A 2× interpolator filter (FIR85) enables
the AD9161/AD9162 to be configured for lower data rates and
converter clocking to reduce the overall system power and ease
the filtering requirements. In Mix-Mode™ operation, the AD9161/
AD9162 can reconstruct RF carriers in the second and third
Nyquist zones up to 7.5 GHz while still maintaining exceptional
dynamic range. The output current can be programmed from
8 mA to 38.76 mA. The AD9161/AD9162 data interface consists
of up to eight JESD204B serializer/deserializer (SERDES) lanes
that are programmable in terms of lane speed and number of
lanes to enable application flexibility.
A serial peripheral interface (SPI) can configure the AD9161/
AD9162 and monitor the status of all registers. The AD9161/
AD9162 are offered in an 165-ball, 8.0 mm × 8.0 mm, 0.5 mm
pitch, CSP_BGA package and in an 169-ball, 11 mm × 11 mm,
0.8 mm pitch, CSP_BGA package, including a leaded ball
option for the AD9162.
The AD9161/AD91621 are high performance, 11-bit/16-bit
PRODUCT HIGHLIGHTS
digital-to-analog converters (DACs) that supports data rates to
6 GSPS. The DAC core is based on a quad-switch architecture
coupled with a 2× interpolator filter that enables an effective
DAC update rate of up to 12 GSPS in some modes. The high
dynamic range and bandwidth makes these DACs ideally suited
for the most demanding high speed radio frequency (RF) DAC
applications.
1. High dynamic range and signal reconstruction bandwidth
supports RF signal synthesis of up to 7.5 GHz.
2. Up to eight lanes JESD204B SERDES interface flexible in
terms of number of lanes and lane speed.
3. Bandwidth and dynamic range to meet DOCSIS 3.1
compliance with margin.
FUNCTIONAL BLOCK DIAGRAM
RESET IRQ
ISET VREF
SDIO
SDO
CS
SCLK
SERDIN0±
SERDIN7±
SYNCOUT±
SYSREF±
SPI
JESD
HB
HB
AD9161/AD9162
HB
NCO
VREF
NRZ RZ MIX
INV
SINC
DAC
CORE
OUTPUT±
HB
TO JESD
CLOCK
2×,
TO DATAPATH
DISTRIBUTION
4×,
TX_ENABLE
Figure 1.
CLK±
1 Protected by U.S. Patents 6,842,132 and 7,796,971.
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com




AD9162 pdf, 반도체, 판매, 대치품
AD9161/AD9162
Data Sheet
Parameter
DVDD_1P2
PLL_LDO_VDD12
PLL_CLK_VDD12
SYNC_VDD_3P3
BIAS_VDD_1P2
Test Conditions/Comments
Can connect to PLL_LDO_VDD12
Can connect to VDD_1P2
Min
1.14
1.14
1.14
3.135
1.14
Typ
1.2
1.2
1.2
3.3
1.2
Max
1.326
1.326
1.326
3.465
1.326
Unit
V
V
V
V
V
1 VDDx is VDD12_CLK, DVDD, VDD_1P2, DVDD_1P2, and PLL_LDO_VDD12. Any clock speed over 5.1 GSPS requires a maximum junction temperature of 105°C to avoid
damage to the device. See Table 11 for details on maximum junction temperature permitted for certain clock speeds.
2 See Table 2 for the complete details on the guaranteed speed performance.
3 FIR85 is the finite impulse response filter with 85 dB digital attenuation that implements 2× NRZ mode.
4 The adjusted DAC update rate is calculated as fDAC divided by the minimum required interpolation factor. For the AD9162, the minimum interpolation factor is 1.
Therefore, with fDAC = 6 GSPS, fDAC adjusted = 6 GSPS. For the AD9161, the minimum interpolation is 2×. Therefore, with fDAC = 6 GSPS, fDAC adjusted = 3 GSPS. When
FIR85 is enabled, which puts the device into 2× NRZ mode, fDAC = 2 × (DAC clock input frequency), and the minimum interpolation increases to 2× (interpolation
value). Thus, for the AD9162, with FIR85 enabled and DAC clock = 6 GSPS, fDAC = 12 GSPS, minimum interpolation = 2×, and the adjusted DAC update rate = 6 GSPS.
5 See the Clock Input section for more details.
6 For the lowest noise performance, use a separate power supply filter network for the VDD12_CLK and the VDD12A pins.
7 IOVDD can range from 1.8 V to 3.3 V, with ±5% tolerance.
DAC INPUT CLOCK OVERCLOCKING SPECIFICATIONS
VDD25_DAC = 2.5 V, VDD12A = VDD12_CLK = 1.2 V, VNEG_N1P2 = −1.2 V, DVDD = 1.2 V, IOVDD = 2.5 V, VDD_1P2 =
DVDD_1P2 = PLL_LDO_VDD12 = 1.2 V, SYNC_VDD_3P3 = 3.3 V, IOUTFS = 40 mA, TA = −40°C to +85°C, unless otherwise noted.
Maximum guaranteed speed using the temperatures and voltages conditions as shown in Table 2, where VDDx is VDD12_CLK, DVDD,
VDD_1P2, DVDD_1P2, and PLL_LDO_VDD12. Any DAC clock speed over 5.1 GSPS requires a maximum junction temperature of
105°C to avoid damage to the device. See Table 11 for details on maximum junction temperature permitted for certain clock speeds.
Table 2.
Parameter1
MAXIMUM DAC UPDATE RATE
VDDx = 1.2 V ± 5%
VDDx = 1.2 V ± 2%
VDDx = 1.3 V ± 2%
Test Conditions/Comments
TJMAX = 25°C
TJMAX = 85°C
TJMAX = 105°C
TJMAX = 25°C
TJMAX = 85°C
TJMAX = 105°C
TJMAX = 25°C
TJMAX = 85°C
TJMAX = 105°C
Min Typ Max Unit
6.0 GSPS
5.6 GSPS
5.4 GSPS
6.1 GSPS
5.8 GSPS
5.6 GSPS
6.4 GSPS
6.2 GSPS
6.0 GSPS
1 TJMAX is the maximum junction temperature.
POWER SUPPLY DC SPECIFICATIONS
IOUTFS = 40 mA, TA = −40°C to +85°C, unless otherwise noted. FIR85 is the finite impulse response with 85 dB digital attenuation.
Table 3.
Parameter
8 LANES, 2× INTERPOLATION (80%), 3 GSPS
Analog Supply Currents
VDD25_DAC = 2.5 V
VDD12A = 1.2 V
VDD12_CLK = 1.2 V
VNEG_N1P2 = −1.2 V
Digital Supply Currents
DVDD = 1.2 V
IOVDD1 = 2.5 V
Test Conditions/Comments
Numerically controlled oscillator (NCO) on,
FIR85 on
Includes VDD12_DCD/DLL
Min Typ Max
−119
93.8
3.7
229
−112
621.3
2.5
100
150
279
971
2.7
Unit
mA
µA
mA
mA
mA
mA
Rev. A | Page 4 of 139

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AD9162 전자부품, 판매, 대치품
Data Sheet
AD9161/AD9162
SERIAL PORT AND CMOS PIN SPECIFICATIONS
VDD25_DAC = 2.5 V, VDD12A = VDD12_CLK = 1.2 V, VNEG_N1P2 = −1.2 V, DVDD = 1.2 V, IOVDD = 2.5 V, VDD_1P2 =
DVDD_1P2 = PLL_LDO_VDD12 = 1.2 V, SYNC_VDD_3P3 = 3.3 V, IOUTFS = 40 mA, TA = −40°C to +85°C, unless otherwise noted.
Table 4.
Parameter
WRITE OPERATION
Maximum SCLK Clock Rate
SCLK Clock High
SCLK Clock Low
SDIO to SCLK Setup Time
SCLK to SDIO Hold Time
CS to SCLK Setup Time
SCLK to CS Hold Time
READ OPERATION
SCLK Clock Rate
SCLK Clock High
SCLK Clock Low
SDIO to SCLK Setup Time
SCLK to SDIO Hold Time
CS to SCLK Setup Time
SCLK to SDIO (or SDO) Data Valid Time
CS to SDIO (or SDO) Output Valid to High-Z
INPUTS (SDIO, SCLK, CS, RESET, TX_ENABLE)
Voltage Input
High
Low
Current Input
High
Low
OUTPUTS (SDIO, SDO)
Voltage Output
High
Low
Current Output
High
Low
Symbol
fSCLK, 1/tSCLK
tPWH
tPWL
tDS
tDH
tS
tH
fSCLK, 1/tSCLK
tPWH
tPWL
tDS
tDH
tS
tDV
VIH
VIL
IIH
IIL
VOH
VOL
IOH
IOL
Test Comments/Conditions
See Figure 142
SCLK = 20 MHz
SCLK = 20 MHz
See Figure 141 and Figure 142
Not shown in Figure 141 or
Figure 142
1.8 V ≤ IOVDD ≤ 2.5 V
1.8 V ≤ IOVDD ≤ 2.5 V
1.8 V ≤ IOVDD ≤ 3.3 V
1.8 V ≤ IOVDD ≤ 3.3 V
Min Typ Max Unit
100
3.5
4
42
1 0.5
91
9 0.5
MHz
ns
ns
ns
ns
ns
ns
20 MHz
20 ns
20 ns
10 ns
5 ns
10 ns
17 ns
45 ns
0.7 × IOVDD
−150
V
0.3 × IOVDD V
75 µA
µA
0.8 × IOVDD
4
4
V
0.2 × IOVDD V
mA
mA
Rev. A | Page 7 of 139

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