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AD9152 데이터시트 PDF




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기능 Digital-to-Analog Converter
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AD9152 데이터시트, 핀배열, 회로
Data Sheet
Dual, 16-Bit, 2.25 GSPS, TxDAC+
Digital-to-Analog Converter
AD9152
FEATURES
GENERAL DESCRIPTION
Supports input data rates up to 1.125 GSPS
Proprietary low spurious and distortion design
Single carrier LTE 20 MHz bandwidth (BW), ACLR = 77 dBc
at 180 MHz IF
SFDR = 72 dBc at 150 MHz IF, −6 dBFS
Flexible 4-lane JESD204B interface
Multiple chip synchronization
Fixed latency
Data generator latency compensation
Selectable 1×, 2×, 4×, and 8× interpolation filter
Low power architecture
Input signal power detection
Emergency stop for downstream analog circuitry protection
Transmit enable function allows extra power saving
High performance, low noise, phase-locked loop (PLL) clock
multiplier
Digital inverse sinc filter and programmable finite impulse
response (FIR) filter
Low power: 1223 mW at 1.5 GSPS, 1406 mW at 2.0 GSPS, full
operating conditions
56-lead LFCSP with exposed pad
APPLICATIONS
Wireless communications
Multicarrier LTE and GSM base stations
Wideband repeaters
Software defined radios
Wideband communications
Point to point microwave radios
LMDS/MMDS
Transmit diversity, multiple input/multiple output (MIMO)
Instrumentation
Automated test equipment
The AD9152 is a dual, 16-bit, high dynamic range digital-to-
analog converter (DAC) that provides a maximum sample rate of
2.25 GSPS, permitting a multicarrier generation up to the Nyquist
frequency. The DAC outputs are optimized to interface seam-
lessly with the ADRF6720 analog quadrature modulator (AQM)
from Analog Devices, Inc. An optional 3-wire or 4-wire serial
port interface (SPI) provides for programming/readback of
many internal parameters. The full-scale output current can be
programmed over a range of 4 mA to 20 mA. The AD9152 is
available in a 56-lead LFCSP. The AD9152 is a member of the
TxDAC+® family.
PRODUCT HIGHLIGHTS
1. Ultrawide signal bandwidth enables emerging wideband
and multiband wireless applications.
2. Advanced low spurious and distortion design techniques
provide high quality synthesis of wideband signals from
baseband to high intermediate frequencies.
3. JESD204B Subclass 1 support simplifies multichip
synchronization in software and hardware design.
4. Fewer pins for data interface width with the serializer/
deserializer (SERDES) JESD204B four-lane interface.
5. Programmable transmit enable function allows easy design
balance between power consumption and wake-up time.
6. Small package size with an 8 mm × 8 mm footprint.
FUNCTIONAL BLOCK DIAGRAM
RF
OUTPUT
CTRL
AMP
AMP
VGA
QUAD MOD
ADRF6720
0/90° PHASE
SHIFTER
LPF
DUAL
DAC
DAC
DAC
JESD204B
SYNC
SYSREF
LO_IN MOD_SPI
Figure 1.
AD9152
DAC
SPI
Rev. 0
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com




AD9152 pdf, 반도체, 판매, 대치품
Data Sheet
Step 6: Optional Error Monitoring ...........................................70
Board Level Hardware Considerations ........................................71
Power Supply Recommendations .............................................71
JESD204B Serial Interface Inputs (SERDIN0± to SERDIN3±) .. 71
Register Map and Descriptions .....................................................74
REVISION HISTORY
4/15—Revision 0: Initial Version
AD9152
Device Configuration Register Map.........................................74
Device Configuration Register Descriptions ..........................80
Outline Dimensions......................................................................104
Ordering Guide .........................................................................104
Rev. 0 | Page 3 of 104

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AD9152 전자부품, 판매, 대치품
AD9152
Data Sheet
DIGITAL SPECIFICATIONS
AVDD33 = 3.3 V, SIOVDD33 = 3.3 V, IOVDD = 1.8 V, DVDD12 = 1.2 V, CVDD12 = 1.2 V, PVDD12 = 1.2 V, PLLVDD12 = 1.2 V,
SVDD12 = 1.2 V, SDVDD12 = 1.2 V, VTT = 1.2 V, TA = −40°C to +85°C, IOUTFS = 20 mA, unless otherwise noted.
Table 2.
Parameter
CMOS INPUT LOGIC LEVEL
Input Voltage Logic
High
Low
CMOS OUTPUT LOGIC LEVEL
Output Voltage Logic
High
Low
MAXIMUM DAC UPDATE RATE1
ADJUSTED DAC UPDATE RATE
INTERFACE3
Number of JESD204B Lanes
JESD204B Serial Interface Speed
Minimum
Maximum
DAC CLOCK INPUT (DACCLK±)
Differential Peak-to-Peak Voltage
Common-Mode Voltage
Maximum Clock Rate
REFERENCE CLOCK INPUT (REFCLK±)
Differential Peak-to-Peak Voltage
Common-Mode Voltage
Input Clock Frequency (PLL
Mode)
SYSTEM REFERENCE INPUT
(SYSREF±)
Differential Peak-to-Peak
Voltage
Common-Mode Voltage
SYSREF± Frequency4
SYSREF± TO DAC CLOCK5
Setup Time
Hold Time
Keep Out Window
Symbol
VIN
VOUT
tSSD
tHSD
KOW
Test Conditions/Comments
1.8 V IOVDD 3.3 V
1.8 V IOVDD 3.3 V
1.8 V IOVDD 3.3 V
1.8 V IOVDD 3.3 V
DVDD12 = CVDD12 = PVDD12 =
1.3 V ± 2%
1× interpolation2
2× interpolation
4× interpolation
8× interpolation
DVDD12 = CVDD12 = PVDD12 =
1.3 V ± 2%
1× interpolation
2× interpolation
4× interpolation
8× interpolation
SVDD12 = SDVDD12 = PLLVDD12 =
1.3 V ± 2%
Per lane
Per lane
Self biased input, ac-coupled
DVDD12 = CVDD12 = PVDD12 =
1.3 V ± 2%
Self biased input, ac-coupled
6 GHz ≤ fVCO ≤ 12 GHz
SYSREF± differential swing = 1.2 V,
slew rate = 6.3 V/ns, hysteresis off (ac-
coupled, and 0 V, 0.6 V, 1.25 V, 2.0 V dc-
coupled common-mode voltages)
Min
0.7 × IOVDD
0.7 × IOVDD
1238
2250
2250
2250
1238
1125
562.5
281.25
12.38
400
2250
400
70
400
0
−6
224
Typ
4
1000
600
1000
600
1000
218
Max
0.3 × IOVDD
0.3 × IOVDD
1.44
2000
2000
1000
2000
2000
fDATA/(K × S)
Unit
V
V
V
V
MSPS
MSPS
MSPS
MSPS
MSPS
MSPS
MSPS
MSPS
Lanes
Gbps
Gbps
mV
mV
MHz
mV
mV
MHz
mV
mV
Hz
ps
ps
ps
Rev. 0 | Page 6 of 104

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