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부품번호 AD9164 기능
기능 RF DAC and Direct Digital Synthesizer
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AD9164 데이터시트, 핀배열, 회로
Data Sheet
16-Bit, 12 GSPS,
RF DAC and Direct Digital Synthesizer
AD9164
FEATURES
fast hop modes, phase coherent fast frequency hopping (FFH) is
DAC update rate up to 12 GSPS (minimum)
enabled, with several modes to support multiple applications.
Direct RF synthesis at 6 GSPS (minimum)
In baseband mode, wide analog bandwidth capability combines
DC to 2.5 GHz in baseband mode
with high dynamic range to support DOCSIS 3.1 cable infrastruc-
DC to 6 GHz in 2× nonreturn-to-zero (NRZ) mode
ture compliance from the minimum of one carrier up to the full
1.5 GHz to 7.5 GHz in Mix-Mode
maximum spectrum of 1.791 GHz of signal bandwidth. A 2×
Bypassable interpolation
interpolator filter (FIR85) enables the AD9164 to be configured
2×, 3×, 4×, 6×, 8×, 12×, 16×, 24×
for lower data rates and converter clocking to reduce the overall
Excellent dynamic performance
system power and ease the filtering requirements. In Mix-Mode™
APPLICATIONS
Broadband communications systems
DOCSIS 3.1 cable modem termination system (CMTS)/
video on demand (VOD)/edge quadrature amplitude
modulation (EQAM)
Wireless communications infrastructure
W-CDMA, LTE, LTE-A, point to point
GENERAL DESCRIPTION
operation, the AD9164 can reconstruct RF carriers in the second
and third Nyquist zones up to 7.5 GHz while still maintaining
exceptional dynamic range. The output current can be programmed
from 8 mA to 38.76 mA. The AD9164 data interface consists of
up to eight JESD204B serializer/deserializer (SERDES) lanes
that are programmable in terms of lane speed and number of
lanes to enable application flexibility.
An SPI interface configures the AD9164 and monitors the status of
all registers. The AD9164 is offered in an 165-ball, 8 mm × 8 mm,
The AD91641 is a high performance, 16-bit digital-to-analog
0.5 mm pitch CSP_BGA package, and an 169-ball, 11 mm × 11 mm,
converter (DAC) and direct digital synthesizer (DDS) that
0.8 mm pitch, CSP_BGA package, including a leaded ball option.
supports update rates to 6 GSPS. The DAC core is based on a
quad-switch architecture coupled with a 2× interpolator filter
that enables an effective DAC update rate of up to 12 GSPS in
some modes. The high dynamic range and bandwidth makes
these DACs ideally suited for the most demanding high speed
radio frequency (RF) DAC applications.
The DDS consists of a bank of 32, 32-bit numerically controlled
oscillators (NCOs), each with its own phase accumulator. When
combined with a 100 MHz serial peripheral interface (SPI) and
PRODUCT HIGHLIGHTS
1. High dynamic range and signal reconstruction bandwidth
supports RF signal synthesis of up to 7.5 GHz.
2. Up to eight lanes JESD204B SERDES interface flexible in
terms of number of lanes and lane speed.
3. Bandwidth and dynamic range to meet DOCSIS 3.1
compliance and multiband wireless communications
standards with margin.
FUNCTIONAL BLOCK DIAGRAM
RESET IRQ
ISET VREF
SDIO
SDO
CS
SCLK
SERDIN0±
SERDIN7±
SYNCOUT±
SYSREF±
SPI
JESD
HB
HB
AD9164
HB
NCO
VREF
NRZ RZ MIX
INV
SINC
DAC
CORE
OUTPUT±
HB
TO JESD
CLOCK
2×,
TO DATAPATH
DISTRIBUTION
4×,
TX_ENABLE
Figure 1.
CLK±
1 Protected by U.S. Patents 6,842,132 and 7,796,971.
Rev. 0
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com




AD9164 pdf, 반도체, 판매, 대치품
Data Sheet
AD9164
SPECIFICATIONS
DC SPECIFICATIONS
VDD25_DAC = 2.5 V, VDD12A = VDD12_CLK = 1.2 V, VNEG_N1P2 = −1.2 V, DVDD = 1.2 V, IOVDD = 2.5 V, VDD_1P2 =
DVDD_1P2 = PLL_LDO_VDD12 = 1.2 V, SYNC_VDD_3P3 = 3.3 V, DAC output full-scale current (IOUTFS) = 40 mA, and TA = −40°C to
+85°C, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
DAC Update Rate
Minimum
Maximum
Adjusted4
ACCURACY
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
ANALOG OUTPUTS
Gain Error (with Internal Reference)
Full-Scale Output Current
Minimum
Maximum
DAC CLOCK INPUT (CLK+, CLK−)
Differential Input Power
Common-Mode Voltage
Input Impedance1
TEMPERATURE DRIFT
Gain
Reference Voltage
REFERENCE
Internal Reference Voltage
ANALOG SUPPLY VOLTAGES
VDD25_DAC
VDD12A2
VDD12_CLK2
VNEG_N1P2
DIGITAL SUPPLY VOLTAGES
DLL_VDD_1P2
DVDD
IOVDD3
SERDES SUPPLY VOLTAGES
VDD_1P2
VTT_1P2
DVDD_1P2
PLL_LDO_VDD12
PLL_CLK_VDD12
SYNC_VDD_3P3
BIAS_VDD_1P2
Test Conditions/Comments
VDDx1 = 1.3 V ± 2%2
VDDx1 = 1.3 V ± 2%2, FIR853 2× interpolator enabled
VDDx1 = 1.3 V ± 2%2
RSET = 9.76 kΩ
RSET = 9.76 kΩ
RLOAD = 90 Ω differential on-chip
AC-coupled
3 GSPS input clock
Can connect to DVDD
Includes VDD12_DCD/DLL
Can connect to VDD_1P2
Can connect to PLL_LDO_VDD12
Can connect to VDD_1P2
Min
16
6
12
6
7.37
35.8
−20
2.375
1.14
1.14
−1.26
1.14
1.14
1.71
1.14
1.14
1.14
1.14
1.14
3.135
1.14
Typ
6.4
12.8
6.4
±2.7
±1.7
−1.7
8
38.76
0
0.6
90
105
75
1.19
2.5
1.2
1.2
−1.2
1.2
1.2
2.5
1.2
1.2
1.2
1.2
1.2
3.3
1.2
Max Unit
Bit
1.5 GSPS
GSPS
GSPS
GSPS
LSB
LSB
%
8.57 mA
41.3 mA
+10 dBm
V
ppm/°C
ppm/°C
V
2.625
1.326
1.326
−1.14
V
V
V
V
1.326
1.326
3.465
V
V
V
1.326
1.326
1.326
1.326
1.326
3.465
1.326
V
V
V
V
V
V
V
1 See the Output Stage Configuration section for more details.
2 For the lowest noise performance, use a separate power supply filter network for the VDD12_CLK and the VDD12A pins.
3 IOVDD can range from 1.8 V to 3.3 V, with ±5% tolerance.
4 The adjusted DAC update rate is calculated as fDAC divided by the minimum required interpolation factor. For the AD9164, the minimum interpolation factor is 1.
Therefore, with fDAC = 6 GSPS, fDAC adjusted = 6 GSPS. When FIR85 is enabled, which puts the device into 2× NRZ mode, fDAC = 2 × (DAC clock input frequency), and the
minimum interpolation increases to 2× (interpolation value). Thus, for the AD9164, with FIR85 enabled and DAC clock = 6 GSPS, fDAC = 12 GSPS, minimum interpolation = 2×, and
the adjusted DAC update rate = 6 GSPS.
Rev. 0 | Page 3 of 134

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AD9164 전자부품, 판매, 대치품
AD9164
Data Sheet
Parameter
POWER DISSIPATION
3 GSPS
2× NRZ Mode, 6×, FIR85 Enabled, NCO On
NRZ Mode, 24×, FIR85 Disabled, NCO On
5 GSPS
NRZ Mode, 8×, FIR85 Disabled, NCO On
NRZ Mode, 16×, FIR85 Disabled, NCO On
2× NRZ Mode, 6×, FIR85 Enabled, NCO On
Test Conditions/Comments
Using 80%, 3× filter, eight-lane JESD204B
Using 80%, 2× filter, one-lane JESD204B
Using 80%, 2× filter, eight-lane JESD204B
Using 80%, 2× filter, eight-lane JESD204B
Using 80%, 3× filter, eight-lane JESD204B
1 IOVDD can range from 1.8 V to 3.3 V, with ±5% tolerance.
Min Typ Max Unit
2.1 W
1.3 W
2.18 W
2.09 W
2.65 W
SERIAL PORT AND CMOS PIN SPECIFICATIONS
VDD25_DAC = 2.5 V, VDD12A = VDD12_CLK = 1.2 V, VNEG_N1P2 = −1.2 V, DVDD = 1.2 V, IOVDD = 2.5 V, VDD_1P2 =
DVDD_1P2 = PLL_LDO_VDD12 = 1.2 V, SYNC_VDD_3P3 = 3.3 V, IOUTFS = 40 mA, TA = −40°C to +85°C, unless otherwise noted.
Table 4.
Parameter
WRITE OPERATION
Maximum SCLK Clock Rate
SCLK Clock High
SCLK Clock Low
SDIO to SCLK Setup Time
SCLK to SDIO Hold Time
CS to SCLK Setup Time
SCLK to CS Hold Time
READ OPERATION
SCLK Clock Rate
SCLK Clock High
SCLK Clock Low
SDIO to SCLK Setup Time
SCLK to SDIO Hold Time
CS to SCLK Setup Time
SCLK to SDIO (or SDO) Data Valid Time
CS to SDIO (or SDO) Output Valid to High-Z
INPUTS (SDIO, SCLK, CS, RESET, TX_ENABLE)
Voltage Input
High
Low
Current Input
High
Low
OUTPUTS (SDIO, SDO)
Voltage Output
High
Low
Current Output
High
Low
Symbol
fSCLK, 1/tSCLK
tPWH
tPWL
tDS
tDH
tS
tH
fSCLK, 1/tSCLK
tPWH
tPWL
tDS
tDH
tS
tDV
VIH
VIL
IIH
IIL
VOH
VOL
IOH
IOL
Test Comments/Conditions
See Figure 90
SCLK = 20 MHz
SCLK = 20 MHz
See Figure 89
Not shown in Figure 89 or Figure 90
1.8 V ≤ IOVDD ≤ 2.5 V
1.8 V ≤ IOVDD ≤ 2.5 V
1.8 V ≤ IOVDD ≤ 3.3 V
1.8 V ≤ IOVDD ≤ 3.3 V
Min Typ Max Unit
100
3.5
4
42
1 0.5
91
9 0.5
MHz
ns
ns
ns
ns
ns
ns
20 MHz
20 ns
20 ns
10 ns
5 ns
10 ns
17 ns
45 ns
0.7 × IOVDD
−150
V
0.3 × IOVDD V
75 µA
µA
0.8 × IOVDD
4
4
V
0.2 × IOVDD V
mA
mA
Rev. 0 | Page 6 of 134

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