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부품번호 AD9363 기능
기능 RF Agile Transceiver
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AD9363 데이터시트, 핀배열, 회로
Data Sheet
FEATURES
Radio frequency (RF) 2 × 2 transceiver with integrated 12-bit
DACs and ADCs
Wide bandwidth: 325 MHz to 3.8 GHz
Supports time division duplex (TDD) and frequency division
duplex (FDD) operation
Tunable channel bandwidth (BW): up to 20 MHz
Receivers: 6 differential or 12 single-ended inputs
Superior receiver sensitivity with a noise figure: 3 dB
Receive (Rx) gain control
Real-time monitor and control signals for manual gain
Independent automatic gain control (AGC)
Dual transmitters: 4 differential outputs
Highly linear broadband transmitter
Transmit (Tx) error vector magnitude (EVM): −34 dB
Tx noise: ≤−157 dBm/Hz noise floor
Tx monitor: 66 dB dynamic range with 1 dB accuracy
Integrated fractional N synthesizers
2.4 Hz local oscillator (LO) step size
CMOS/LVDS digital interface
APPLICATIONS
3G enterprise femtocell base stations
4G femtocell base stations
Wireless video transmission
GENERAL DESCRIPTION
The AD9363 is a high performance, highly integrated RF agile
transceiver designed for use in 3G and 4G femtocell applications.
Its programmability and wideband capability make it ideal for a
broad range of transceiver applications. The device combines an
RF front end with a flexible mixed-signal baseband section and
integrated frequency synthesizers, simplifying design-in by
providing a configurable digital interface to a processor. The
AD9363 operates in the 325 MHz to 3.8 GHz range, covering
most licensed and unlicensed bands. Channel bandwidths from
less than 200 kHz to 20 MHz are supported.
The two independent direct conversion receivers have state-of-
the-art noise figure and linearity. Each Rx subsystem includes
independent automatic gain control (AGC), dc offset correction,
quadrature correction, and digital filtering, thereby eliminating
the need for these functions in the digital baseband. The AD9363
also has flexible manual gain modes that can be externally
controlled. Two high dynamic range ADCs per channel digitize
the received I and Q signals and pass them through configurable
decimation filters and 128-tap finite impulse response (FIR)
filters to produce a 12-bit output signal at the appropriate
Rev. D
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
RF Agile Transceiver
AD9363
FUNCTIONAL BLOCK DIAGRAM
RX1B_P,
RX1B_N
RX1A_P,
RX1A_N
RX1C_P,
RX1C_N
RX2B_P,
RX2B_N
RX2A_P,
RX2A_N
RX2C_P,
RX2C_N
AD9363
ADC
RX LO
ADC
P0_D11/
TX_D5_x TO P0_D0/
TX_D0_x
TX_MON1
TX1A_P,
TX1A_N
TX1B_P,
TX1B_N
TX_MON2
TX2A_P,
TX2A_N
TX2B_P,
TX2B_N
SPI
CTRL
TX LO
CTRL
DAC
DAC
GPO
PLLs
P1_D11/
RX_D5_x TO P1_D0/
RX_D0_x
RADIO
SWITCHING
CLK_OUT
AUXADC AUXDACx XTALN
NOTES
1. SPI, CTRL, P0_D11/TX_D5_x TO P0_D0/TX_D0_x, P1_D11/
RX_D5_x TO P1_D0/RX_D0_x, AND RADIO SWITCHING
CONTAIN MULTIPLE PINS.
Figure 1.
sample rate.
The transmitters use a direct conversion architecture that achieves
high modulation accuracy with ultralow noise. This transmitter
design produces a best-in-class Tx EVM of −34 dB, allowing
significant system margin for the external power amplifier (PA)
selection. The on-board Tx power monitor can be used as a
power detector, enabling highly accurate Tx power
measurements.
The fully integrated phase-locked loops (PLLs) provide low
power fractional N frequency synthesis for all receive and
transmit channels. Channel isolation, demanded by FDD
systems, is integrated into the design. All voltage controlled
oscillators (VCOs) and loop filter components are integrated.
The core of the AD9363 can be powered directly from a 1.3 V
regulator. The IC is controlled via a standard 4-wire serial port
and four real-time I/O control pins. Comprehensive power-down
modes are included to minimize power consumption during
normal use. The AD9363 is packaged in a 10 mm × 10 mm,
144-ball chip scale package ball grid array (CSP_BGA).
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com




AD9363 pdf, 반도체, 판매, 대치품
AD9363
Data Sheet
Parameter1
RX2x_x to RX1x_x Isolation
RX2A_x to RX1A_x, RX2C_x to RX1C_x
RX2B_x to RX1B_x
RECEIVERS, 3.5 GHz
Noise Figure
Third-Order Input Intermodulation
Intercept Point
Second-Order Input Intermodulation
Intercept Point
Local Oscillator (LO) Leakage
Quadrature
Gain Error
Phase Error
Modulation Accuracy (EVM)
Input Return Loss
RX1x_x to RX2x_x Isolation
RX1A_x to RX2A_x, RX1C_x to RX2C_x
RX1B_x to RX2B_x
RX2x_x to RX1x_x Isolation
RX2A_x to RX1A_x, RX2C_x to RX1C_x
RX2B_x to RX1B_x
TRANSMITTERS, GENERAL
Center Frequency
Tx Bandwidth
Power Control Range
Power Control Resolution
TRANSMITTERS, 800 MHz
Output Return Loss
Maximum Output Power
Modulation Accuracy (EVM)
Third-Order Output Intermodulation
Intercept Point
Carrier Leakage
Noise Floor
Isolation
TX1x_x to TX2x_x
TX2x_x to TX1x_x
TRANSMITTERS, 2.4 GHz
Output Return Loss
Maximum Output Power
Modulation Accuracy (EVM)
Third-Order Output Intermodulation
Intercept Point
Carrier Leakage
Noise Floor
Isolation
TX1x_x to TX2x_x
TX2x_x to TX1x_x
TRANSMITTERS, 3.5 GHz
Output Return Loss
Maximum Output Power
Modulation Accuracy (EVM)
Symbol Min Typ Max Unit
Test Conditions/Comments
65 dB
50 dB
NF 3.3 dB Maximum Rx gain
IIP3 −15 dBm Maximum Rx gain
IIP2 44 dBm Maximum Rx gain
−100
dBm At Rx front-end input
0.2 %
0.2 Degrees
−34 dB 40 MHz reference clock
S11 −10 dB
60 dB
48 dB
60 dB
48 dB
325 3800 MHz
20 MHz
90 dB
0.25 dB
S22
OIP3
−10
8
−34
23
−50
−32
−157
dB
dBm 1 MHz tone into 50 Ω load
dB 19.2 MHz reference clock
dBm
dBc
dBc
dBm/Hz
0 dB attenuation
40 dB attenuation
90 MHz offset
50 dB
50 dB
S22
OIP3
−10
7.5
−34
19
−50
−32
−156
dB
dBm 1 MHz tone into 50 Ω load
dB 40 MHz reference clock
dBm
dBc
dBc
dBm/Hz
0 dB attenuation
40 dB attenuation
90 MHz offset
50 dB
50 dB
S22 −10 dB
7.0 dBm 1 MHz tone into 50 Ω load
−34 dB 40 MHz reference clock
Rev. D | Page 4 of 32

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AD9363 전자부품, 판매, 대치품
Data Sheet
AD9363
Parameter1
DIGITAL DATA TIMING (CMOS),
VDD_INTERFACE = 2.5 V
DATA_CLK_x Clock Period
DATA_CLK_x and FB_CLK_x
Pulse Width
Tx Data
Setup to FB_CLK_x
Hold to FB_CLK_x
DATA_CLK_x to Data Bus
Output Delay
DATA_CLK_x to
RX_FRAME_x Delay
Pulse Width
ENABLE
TXNRX
TXNRX Setup to ENABLE
Bus Turnaround Time
Before Rx
After Rx
Capacitive Load
Capacitive Input
DIGITAL DATA TIMING (LVDS)
DATA_CLK_x Clock Period
DATA_CLK_x and FB_CLK_x
Pulse Width
Tx Data
Setup to FB_CLK_x
Hold to FB_CLK_x
DATA_CLK_x to Data Bus
Output Delay
DATA_CLK_x to
RX_FRAME_x Delay
Pulse Width
ENABLE
TXNRX
TXNRX Setup to ENABLE
Bus Turnaround Time
Before Rx
After Rx
Capacitive Load
Capacitive Input
SUPPLY CHARACTERISTICS
1.3 V Main Supply
VDD_INTERFACE Supply
CMOS
LVDS
VDD_GPO Supply
Symbol Min
tCP 16.276
tMP 45% of tCP
tSTX
tHTX
tDDRX
tDDDV
1
0
0.25
0.25
tENPW
tTXNRXPW
tTXNRXSU
tRPRE
tRPST
tCP
tCP
0
2 × tCP
2 × tCP
tCP 4.069
tMP 45% of tCP
tSTX
tHTX
tDDRX
tDDDV
1
0
0
0
tENPW
tTXNRXPW
tTXNRXSU
tRPRE
tRPST
tCP
tCP
0
2 × tCP
2 × tCP
1.267
1.2
1.8
1.3
Current Consumption
VDDx, Sleep Mode
VDD_GPO
Typ
3
3
3
3
1.3
3.3
180
50
Max
55% of tCP
1.25
1.25
55% of tCP
1.5
1.0
1.33
2.5
2.5
3.465
Unit Test Conditions/Comments
ns 61.44 MHz
ns
TX_FRAME_x, P0_Dx, and P1_Dx
ns
ns
ns
ns
ns
ns FDD independent ENSM mode
ns TDD ENSM mode
TDD mode
ns
ns
pF
pF
ns 245.76 MHz
ns
TX_FRAME_x and TX_Dx
ns
ns
ns
ns
ns
ns FDD independent ENSM mode
ns TDD ENSM mode
ns
ns
pF
pF
V
V
V
V When unused, must be set to
1.3 V
µA Sum of all input currents
μA No load
1 When referencing a single function of a multifunction pin in the parameters, only the portion of the pin name that is relevant to the specification is listed. For full pin
names of multifunction pins, refer to the Pin Configuration and Function Descriptions section.
Rev. D | Page 7 of 32

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