PDF AD9371 Data sheet ( Hoja de datos )

Número de pieza	AD9371
Descripción	Dual RF Transceiver
Fabricantes	Analog Devices
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No Preview Available ! Data Sheet Integrated, Dual RF Transceiver with Observation Path AD9371 FEATURES Dual differential transmitters (Tx) Dual differential receivers (Rx) Observation receiver (ORx) with 2 inputs Sniffer receiver (SnRx) with 3 inputs Tunable range: 300 MHz to 6000 MHz Tx synthesis bandwidth (BW) to 250 MHz Rx BW: 8 MHz to 100 MHz Supports frequency division duplex (FDD) and time division duplex (TDD) operation Fully integrated independent fractional-N radio frequency (RF) synthesizers for Tx, Rx, ORx, and clock generation JESD204B digital interface APPLICATIONS 3G/4G micro and macro base stations (BTS) 3G/4G multicarrier picocells FDD and TDD active antenna systems Microwave, nonline of sight (NLOS) backhaul systems GENERAL DESCRIPTION The AD9371 is a highly integrated, wideband RF transceiver offering dual channel transmitters and receivers, integrated synthesizers, and digital signal processing functions. The IC delivers a versatile combination of high performance and low power consumption required by 3G/4G micro and macro BTS equipment in both FDD and TDD applications. The AD9371 operates from 300 MHz to 6000 MHz, covering most of the licensed and unlicensed cellular bands. The IC supports receiver bandwidths up to 100 MHz. It also supports observation receiver and transmit synthesis bandwidths up to 250 MHz to accommodate digital correction algorithms. The transceiver consists of wideband direct conversion signal paths with state-of-the-art noise figure and linearity. Each complete receiver and transmitter subsystem includes dc offset correction, quadrature error correction (QEC), and programmable digital filters, eliminating the need for these functions in the digital baseband. Several auxiliary functions such as an auxiliary analog- to-digital converter (ADC), auxiliary digital-to-analog converters (DACs), and general-purpose input/outputs (GPIOs) are integrated to provide additional monitoring and control capability. An observation receiver channel with two inputs is included to monitor each transmitter output and implement interference mitigation and calibration applications. This channel also connects to three sniffer receiver inputs that can monitor radio activity in different bands. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityis assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. RX1+ RX1– RX2+ RX2– RX_EXTLO+ RX_EXTLO– TX1+ TX1– TX2+ TX2– FUNCTIONAL BLOCK DIAGRAM AD9371 RX1 RX2 LPF LPF ADC ADC EXTERNAL OPTION LO GENERATOR RF SYNTHESIZER DECIMATION, pFIR, DC OFFSET QEC, TUNING, RSSI, OVERLOAD MICRO- CONTROLLER TX1 TX2 LPF LPF DAC DAC SPI PORT pFIR, QEC, INTERPOLATION TX_EXTLO+ TX_EXTLO– EXTERNAL OPTION LO GENERATOR LO GENERATOR RF SYNTHESIZER RF SYNTHESIZER ORX1+ ORX1– ORX2+ ORX2– OBSERVATION Rx GPIO AUXADC AUXDAC CLOCK GENERATOR SNRXA+ SNRXA– SNRXB+ SNRXB– SNRXC+ SNRXC– SNIFFER Rx LPF DECIMATION, ADC pFIR, AGC, DC OFFSET, LPF QEC, ADC TUNING, RSSI, OVERLOAD NOTES 1. FOR JESD204B PINS, SEE FIGURE 4. Figure 1. The high speed JESD204B interface supports lane rates up to 6144 Mbps. Four lanes are dedicated to the transmitters and four lanes are dedicated to the receiver and observation receiver channels. The fully integrated phase-locked loops (PLLs) provide high performance, low power fractional-N frequency synthesis for the transmitter, the receiver, the observation receiver, and the clock sections. Careful design and layout techniques provide the isolation demanded in high performance base station applications. All voltage controlled oscillator (VCO) and loop filter components are integrated to minimize the external component count. A 1.3 V supply is required to power the core of the AD9371, and a standard 4-wire serial port controls it. Other voltage supplies provide proper digital interface levels and optimize transmitter and auxiliary converter performance. The AD9371 is packaged in a 12 mm × 12 mm, 196-ball chip scale ball grid array (CSP_BGA). One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com 1 page Data Sheet Parameter Image Rejection 700 MHz LO 2600 MHz LO 3500 MHz LO 5500 MHz LO Input Impedance Tx1 to Rx1 Signal Isolation and Tx2 to Rx2 Signal Isolation 700 MHz LO 2600 MHz LO 3500 MHz LO 5500 MHz LO Tx1 to Rx2 Signal Isolation and Tx2 to Rx1 Signal Isolation 700 MHz LO 2600 MHz LO 3500 MHz LO 5500 MHz LO Rx1 to Rx2 Signal Isolation 700 MHz LO 2600 MHz LO 3500 MHz LO 5500 MHz LO Rx Band Spurs Referenced to RF Input at Maximum Gain Symbol Min Rx LO Leakage at Rx Input at Maximum Gain 700 MHz LO 2600 MHz LO 3500 MHz LO 5500 MHz LO OBSERVATION RECEIVER (ORx) Center Frequency Gain Range Analog Gain Step BW Ripple Deviation from Linear Phase ORx Bandwidth ORx Alias Band Rejection Maximum Recommended Input Power8 300 0 60 Signal-to-Noise Ratio9 700 MHz LO 2600 MHz LO 3500 MHz LO 5500 MHz LO SNR Typ 75 75 75 75 200 68 68 62 60 70 70 62 60 60 60 60 60 −95 −65 −65 −62 −62 1 ±0.5 10 −13 60 60 60 59 Max 6000 18 250 AD9371 Unit Test Conditions/Comments QEC3 active, within Rx BW dB dB dB dB Ω Differential dB dB dB dB dB dB dB dB dB dB dB dB dBm No more than one spur at this level per 10 MHz of Rx BW; excludes harmonics of the reference clock Leakage decreases decibel for decibel with attenuation for first 12 dB dBm dBm dBm dBm MHz dB dB dB Degrees MHz dB dBm dB dB dB dB 250 MHz RF BW, compensated by programmable FIR filter 250 MHz RF BW Due to digital filters Input is a CW7 signal at 0 dB attenuation setting; this level increases decibel for decibel with attenuation Maximum gain at ORx port 200 MHz BW, 245.76 MSPS Rev. A \| Page 5 of 60 5 Page Data Sheet AD9371 TIMING SPECIFICATIONS Table 3. Parameter SERIAL PERIPHERAL INTERFACE (SPI) TIMING SCLK Period SCLK Pulse Width CSB Setup to First SCLK Rising Edge Last SCLK Falling Edge to CSB Hold SDIO Data Input Setup to SCLK SDIO Data Input Hold to SCLK SCLK Falling Edge to Output Data Delay (3- or 4-Wire Mode) Bus Turnaround Time After Baseband Processor (BBP) Drives Last Address Bit Bus Turnaround Time After AD9371 Drives Last Address Bit DIGITAL TIMING TXx_ENABLE Pulse Width RXx_ENABLE Pulse Width JESD204B DATA OUTPUT TIMING Unit Interval Data Rate per Channel (Nonreturn to Zero (NRZ)) Rise Time Fall Time Output Common-Mode Voltage Termination Voltage (VTT) = 1.2 V Differential Output Voltage Short-Circuit Current Differential Termination Impedance Total Jitter Uncorrelated Bounded High Probability Jitter Duty-Cycle Distortion SYSREF_IN Signal Setup Time to DEV_CLK_IN Signal SYSREF_IN Signal Hold Time to DEV_CLK_IN Signal JESD204B DATA INPUT TIMING Unit Interval Data Rate per Channel (NRZ) Input Common-Mode Voltage VTT = 1.2 V Differential Input Voltage VTT Source Impedance Differential Termination Impedance VTT AC-Coupled DC-Coupled Symbol Min Typ Max Unit Test Conditions/Comments tCP 20 tMP 10 tSC 3 tHC 0 tS 2 tH 0 tCO 3 tHZM tH tHZS 0 ns ns ns ns ns ns 8 ns tCO ns tCO ns 10 µs 10 µs UI tR tF VCM VDIFF IDSHORT ZRDIFF UBHPJ DCD tS tH 162.76 1627.6 ps 614.4 6144 Mbps 24 35 ps 20% to 80% in 100 Ω load 24 35 ps 20% to 80% in 100 Ω load 0 1.8 V AC-coupled 735 1135 mV DC-coupled 360 466 770 mV −100 +100 mA 80 100 120 Ω 17 48.8 ps Bit error rate (BER) = 10−15 1.2 24.4 ps 3 8.1 ps 2.5 ns See Figure 2 and Figure 3 −1.5 ns See Figure 2 and Figure 3 UI VCM VDIFF ZTT ZRDIFF 162.76 1627.6 ps 614.4 6144 Mbps 0.05 1.85 V AC-coupled 720 1200 mV DC-coupled 125 750 mV 1.2 30 Ω 80 106 120 Ω 1.27 1.33 V 1.14 1.26 V Rev. A \| Page 11 of 60 11 Page

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