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AD7569 데이터시트 PDF




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부품번호 AD7569 기능
기능 8-Bit Analog I/0 Systems
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AD7569 데이터시트, 핀배열, 회로
a
FEATURES
2 s ADC with Track/Hold
1 s DAC with Output Amplifier
AD7569, Single DAC Output
AD7669, Dual DAC Output
On-Chip Bandgap Reference
Fast Bus Interface
Single or Dual 5 V Supplies
LC2MOS
Complete, 8-Bit Analog I/0 Systems
AD7569/AD7669
AD7569 FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The AD7569/AD7669 is a complete, 8-bit, analog I/O system
on a single monolithic chip. The AD7569 contains a high speed
successive approximation ADC with 2 µs conversion time, a track/
hold with 200 kHz bandwidth, a DAC and an output buffer ampli-
fier with 1 µs settling time. A temperature-compensated 1.25 V
bandgap reference provides a precision reference voltage for the
ADC and the DAC. The AD7669 is similar, but contains two
DACs with output buffer amplifiers.
A choice of analog input/output ranges is available. Using a sup-
ply voltage of +5 V, input and output ranges of zero to 1.25 V
and zero to 2.5 volts may be programmed using the RANGE in-
put pin. Using a ± 5 V supply, bipolar ranges of ± 1.25 V or
± 2.5 V may be programmed.
Digital interfacing is via an 8-bit I/O port and standard micro-
processor control lines. Bus interface timing is extremely fast, al-
lowing easy connection to all popular 8-bit microprocessors. A
separate start convert line controls the track/hold and ADC to
give precise control of the sampling period.
The AD7569/AD7669 is fabricated in Linear-Compatible
CMOS (LC2MOS), an advanced, mixed technology process
combining precision bipolar circuits with low power CMOS
logic. The AD7569 is packaged in a 24-pin, 0.3" wide “skinny”
DIP, a 24-terminal SOIC and 28-terminal PLCC and LCCC
packages. The AD7669 is available in a 28-pin, 0.6" plastic
DIP, 28-terminal SOIC and 28-terminal PLCC package.
AD7669 FUNCTIONAL BLOCK DIAGRAM
PRODUCT HIGHLIGHTS
1. Complete Analog I/O on a Single Chip.
The AD7569/AD7669 provides everything necessary to
interface a microprocessor to the analog world. No external
components or user trims are required and the overall accu-
racy of the system is tightly specified, eliminating the need
to calculate error budgets from individual component
specifications.
2. Dynamic Specifications for DSP Users.
In addition to the traditional ADC and DAC specifications,
the AD7569/AD7669 is specified for ac parameters, includ-
ing signal-to-noise ratio, distortion and input bandwidth.
3. Fast Microprocessor Interface.
The AD7569/AD7669 has bus interface timing compatible
with all modern microprocessors, with bus access and relin-
quish times less than 75 ns and write pulse width less than
80 ns.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
World Wide Web Site: http://www.analog.com
Fax: 617/326-8703
© Analog Devices, Inc., 1996




AD7569 pdf, 반도체, 판매, 대치품
AD7569/AD7669–TIMING CHARACTERISTICS1 (See Figures 8, 10, 12; VDD = 5 V ؎ 5%; VSS = 0 V or –5 V ؎ 5%)
Parameter
Limit at
25؇C (All Grades)
Limit at
TMIN, TMAX
(J, K, A, B Grades)
Limit at
TMIN, TMAX
(S, T Grades)
Units
Test Conditions/Comments
DAC Timing
t1 80
t2 0
t3 0
t4 60
t5 10
80
0
0
70
10
90 ns min WR Pulse Width
0 ns min CS, A/B to WR Setup Time
0 ns min CS, A/B to WR Hold Time
80 ns min Data Valid to WR Setup Time
10 ns min Data Valid to WR Hold Time
ADC Timing
t6
t7
t8
t9
t10
t11
t12
t132
t143
t15
t16
t172
50
110
20
0
0
60
0
60
95
10
60
65
120
60
90
50
130
30
0
0
75
0
75
120
10
75
75
140
75
115
50 ns min ST Pulse Width
150 ns max ST to BUSY Delay
30 ns max BUSY to INT Delay
0 ns min BUSY to CS Delay
0 ns min CS to RD Setup Time
90 ns min RD Pulse Width Determined by t13.
0 ns min CS to RD Hold Time
90 ns max Data Access Time after RD; CL = 20 pF
135 ns max Data Access Time after RD; CL = 100 pF
10 ns min Bus Relinquish Time after RD
85 ns max
85 ns max RD to INT Delay
160 ns max RD to BUSY Delay
90 ns max Data Valid Time after BUSY; CL = 20 pF
135 ns max Data Valid Time after BUSY; CL = 100 pF
NOTES
1Sample tested at +25°C to ensure compliance. All input control signals are specified with tR = tF = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.
2t13 and t17 are measured with the load circuits of Figure 1 and defined as the time required for an output to cross either 0.8 V or 2.4 V.
3tl4 is defined as the time required for the data line to change 0.5 V when loaded with the circuit of Figure 2.
Specifications subject to change without notice.
a. High-Z to VOH
b. High-Z to VOL
Figure 1. Load Circuits for Data Access Time Test
a. VOH to High-Z
b. VOL to High-Z
Figure 2. Load Circuits for Bus Relinquish Time Test
ABSOLUTE MAXIMUM RATINGS
VDD to AGNDDAC or AGNDADC . . . . . . . . . . . . . –0.3 V, +7 V
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +7 V
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +14 V
AGNDDAC or AGNDADC to DGND . . . . –0.3 V, VDD + 0.3 V
AGNDDAC to AGNDADC . . . . . . . . . . . . . . . . . . . . . . . . . ± 5 V
Logic Voltage to DGND . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V
CLK Input Voltage to DGND . . . . . . . . . –0.3 V, VDD + 0.3 V
VOUT (VOUTA, VOUTB) to
AGND1DAC . . . . . . . . . . . . . . . . . VSS – 0.3 V, VDD + 0.3 V
VIN to AGNDADC . . . . . . . . . . . . . . . VSS – 0.3 V, VDD + 0.3 V
NOTE
1Output may be shorted to any voltage in the range VSS to VDD provided that the
power dissipation of the package is not exceeded. Typical short circuit current for
a short to AGND or VSS is 50 mA.
Power Dissipation (Any Package) to +75°C . . . . . . . . 450 mW
Derates above 75°C by . . . . . . . . . . . . . . . . . . . . . 6 mW/°C
Operating Temperature Range
Commercial (J, K) . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Industrial (A, B) . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Extended (S, T) . . . . . . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . +300°C
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other condition above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7569/AD7669 features proprietary ESD protection circuitry, permanent dam-
age may occur on devices subjected to high energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4– REV. B

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AD7569 전자부품, 판매, 대치품
AD7569/AD7669
PIN FUNCTION DESCRIPTION
(Applies to the AD7569 and AD7669 unless otherwise stated.)
Pin
Mnemonic
Description
Pin
Mnemonic
Description
AGNDDAC
Analog Ground for the DAC(s). Separate
ground return paths are provided for the
DAC(s) and ADC to minimize crosstalk.
VOUT
Output Voltage. VOUT is the buffered output
(VOUTA, VOUTB) voltage from the AD7569 DAC. VOUTA and
VOUTB are the buffered DAC output voltages
from the AD7669. Four different output volt-
age ranges can be achieved (see Table I).
VSS
RANGE
Negative Supply Voltage (–5 V for dual sup-
ply or 0 V for single supply). This pin is also
used with the RANGE pin to select the differ-
ent input/output ranges and changes the data
format from binary (VSS = 0 V) to 2s comple-
ment (VSS = –5 V) (see Table I).
Range Selection Input. This is used with the
VSS input to select the different ranges as per
Table I. The range selected applies to both
the analog input voltage of the ADC and the
output voltage from the DAC(s).
RESET
Reset Input (Active Low). This is an asyn-
chronous system reset that clears the DAC
register(s) to all 0s and clears the INT line of
the ADC (i.e., makes the ADC ready for new
conversion). In unipolar operation, this input
sets the output voltage to 0 V; in bipolar
operation, it sets the output to negative full
scale.
DB7 Data Bit 7. Most Significant Bit (MSB).
DB6–DB2
Data Bit 6 to Data Bit 2.
DGND
Digital Ground.
DB1 Data Bit 1.
DB0 Data Bit 0. Least Significant Bit (LSB).
WR Write Input (Edge triggered). This is used in
conjunction with CS to write data into the
AD7569 DAC register. It is used in conjunc-
tion with CS and A/B to write data into the
selected DAC register of the AD7669. Data is
transferred on the rising edge of WR.
CS
RD
ST
BUSY
INT
A/B (AD7669
Only)
CLK
AGNDADC
VIN
VDD
Chip Select Input (Active Low). The device is
selected when this input is active.
READ Input (Active Low). This input must
be active to access data from the part. In the
Mode 2 interface, RD going low starts con-
version. It is used in conjunction with the CS
input (see Digital Interface Section).
Start Conversion (Edge triggered). This is
used when precise sampling is required. The
falling edge of ST starts conversion and drives
BUSY low. The ST signal is not gated with
CS.
BUSY Status Output (Active Low). When
this pin is active, the ADC is performing a
conversion. The input signal is held prior to
the falling edge of BUSY (see Digital Inter-
face Section).
INTERRUPT Output (Active Low). INT go-
ing low indicates that the conversion is com-
plete. INT goes high on the rising edge of CS
or RD and is also set high by a low pulse on
RESET (see Digital Interface Section).
DAC Select Input. This input selects which
DAC register data is written to under control
of CS and WR. With this input low, data is
written to the DACA register; with this input
high, data is written to the DACB register.
A TTL compatible clock signal may be used
to determine the ADC conversion time. Inter-
nal clock operation is achieved by connecting
a resistor and capacitor to ground.
Analog Ground for the ADC.
Analog Input. Various input ranges can be se-
lected (see Table I).
Positive Supply Voltage (+5 V).
Range
0
1
0
1
Table I. Input/Output Ranges
Input/Output
DB0–DB7
VSS Voltage Range Data Format
0V
0 V to +1.25 V
Binary
0 V 0 V to +2.5 V Binary
–5 V ± 1.25 V
2s Complement
–5 V ± 2.5 V
2s Complement
REV. B
–7–

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