AD7177-2 Datasheet PDF - Analog Devices
| Part Number | AD7177-2 | |
| Description | Sigma-Delta ADC | |
| Manufacturers | Analog Devices | |
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Data Sheet
32-Bit, 10 kSPS, Sigma-Delta ADC with 100 µs
Settling and True Rail-to-Rail Buffers
AD7177-2
FEATURES
GENERAL DESCRIPTION
32-bit data output
Fast and flexible output rate: 5 SPS to 10 kSPS
Channel scan data rate of 10 kSPS/channel (100 µs settling)
Performance specifications
19.1 noise free bits at 10 kSPS
20.2 noise free bits at 2.5 kSPS
24.6 noise free bits at 5 SPS
INL: ±1 ppm of FSR
85 dB filter rejection of 50 Hz and 60 Hz with 50 ms settling
User configurable input channels
2 fully differential channels or 4 single-ended channels
Crosspoint multiplexer
On-chip 2.5 V reference (±2 ppm/°C drift)
True rail-to-rail analog and reference input buffers
The AD7177-2 is a 32-bit low noise, fast settling, multiplexed,
2-/4-channel (fully/pseudo differential) Σ-Δ analog-to-digital
converter (ADC) for low bandwidth inputs. It has a maximum
channel scan rate of 10 kSPS (100 µs) for fully settled data. The
output data rates range from 5 SPS to 10 kSPS.
The AD7177-2 integrates key analog and digital signal condition-
ing blocks to allow users to configure an individual setup for
each analog input channel in use. Each feature can be user selected
on a per channel basis. Integrated true rail-to-rail buffers on the
analog inputs and external reference inputs provide easy to drive
high impedance inputs. The precision 2.5 V low drift (2 ppm/°C)
band gap internal reference (with output reference buffer) adds
embedded functionality to reduce external component count.
Internal or external clock
The digital filter allows simultaneous 50 Hz and 60 Hz rejection
Power supply: AVDD1 − AVSS = 5 V, AVDD2 = IOVDD = 2.5 V
at a 27.27 SPS output data rate. The user can switch between
to 5 V
different filter options according to the demands of each
Split supply with AVDD1/AVSS at ±2.5 V
channel in the application. The ADC automatically switches
ADC current: 8.4 mA
Temperature range: −40°C to +105°C
3- or 4-wire serial digital interface (Schmitt trigger on SCLK)
Serial port interface (SPI), QSPI, MICROWIRE, and DSP
compatible
APPLICATIONS
through each selected channel. Further digital processing
functions include offset and gain calibration registers,
configurable on a per channel basis.
The device operates with a 5 V AVDD1 supply, or with ±2.5 V
AVDD1/AVSS, and 2 V to 5 V AVDD2 and IOVDD supplies.
The specified operating temperature range is −40°C to +105°C.
Process control: PLC/DCS modules
The AD7177-2 is available in a 24-lead TSSOP package.
Temperature and pressure measurement
Medical and scientific multichannel instrumentation
Chromatography
FUNCTIONAL BLOCK DIAGRAM
AVDD1 AVDD2 REGCAPA
REF– REF+ REFOUT
IOVDD REGCAPD
CROSSPOINT
MULTIPLEXER
1.8V
LDO
RAIL-TO-RAIL
REFERENCE
INPUT BUFFERS
BUFFERED
PRECISION
REFERENCE
1.8V
LDO
AIN0
AIN1
AIN2
AIN3
AIN4
AVDD RAIL-TO-RAIL
ANALOG INPUT
BUFFERS
Σ-Δ ADC
INT
REF
DIGITAL
FILTER
SERIAL
INTERFACE
AND CONTROL
AVSS
TEMPERATURE
SENSOR
AVSS
GPIO AND
MUX
I/O CONTROL
XTAL AND INTERNAL
CLOCK OSCILLATOR
CIRCUITRY
AD7177-2
GPIO0 GPIO1
XTAL1 XTAL2/CLKIO
Figure 1.
DGND
CS
SCLK
DIN
DOUT/RDY
SYNC/ERROR
Rev. B
Document Feedback
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responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2015–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
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AD7177-2
Data Sheet
SPECIFICATIONS
AVDD1 = 4.5 V to 5.5 V, AVDD2 = 2 V to 5.5 V, IOVDD = 2 V to 5.5 V, AVSS = DGND = 0 V, REF+ = 2.5 V, REF− = AVSS,
internal master clock (MCLK) = 16 MHz, TA = TMIN to TMAX (−40°C to +105°C), unless otherwise noted.
Table 1.
Parameter
ADC SPEED AND PERFORMANCE
Output Data Rate (ODR)
No Missing Codes1
Resolution
Noise
FIR Filter Rejection
ACCURACY
Integral Nonlinearity (INL)
Offset Error2
Offset Drift
Gain Error2
Gain Drift
REJECTION
Power Supply Rejection
Common-Mode Rejection
At DC
At 50 Hz, 60 Hz1
Normal Mode Rejection1
ANALOG INPUTS
Differential Input Range
Absolute Voltage Limits1
Input Buffers Disabled
Input Buffers Enabled
Analog Input Current
Input Buffers Disabled
Input Current
Input Current Drift
Input Buffers Enabled
Input Current
Input Current Drift
Crosstalk
INTERNAL REFERENCE
Output Voltage
Initial Accuracy3
Temperature Coefficient1
0°C to 105°C
−40°C to +105°C
Reference Load Current, ILOAD
Power Supply Rejection
Load Regulation
Test Conditions/Comments
See Table 19 to Table 23
See Table 19 to Table 23
See Table 23
All input buffers disabled
All input buffers enabled
Internal short
Internal short
All input buffers disabled
All input buffers enabled
AVDD1, AVDD2, VIN = 1 V
VIN = 0.1 V
20 Hz output data rate (post filter),
50 Hz ± 1 Hz and 60 Hz ± 1 Hz
50 Hz ± 1 Hz and 60 Hz ± 1 Hz
Internal clock, 20 SPS ODR (postfilter)
External clock, 20 SPS ODR (postfilter)
VREF = (REF+) − (REF−)
External clock
Internal clock (±2.5% clock)
AVDD1 − 0.2 V to AVSS + 0.2 V
AVDD1 to AVSS
1 kHz input
100 nF external capacitor to AVSS
REFOUT, with respect to AVSS
REFOUT, TA = 25°C
AVDD1, AVDD2 (line regulation)
∆VOUT/∆ILOAD
Min
5
32
95
120
71
85
AVSS − 0.05
AVSS
−0.12
−10
Typ
±1
±3.5
±40
±80
±45
±2.5
±0.4
95
90
90
±VREF
±48
±0.75
±4
±30
±75
±1
−120
2.5
±2
±3
90
32
Max
10,000
Unit
SPS
Bits
±3.5
±7.8
±100
±40
±0.75
ppm of FSR
ppm of FSR
µV
nV/°C
ppm of FSR
ppm of FSR
ppm/°C
dB
dB
dB
dB
dB
V
AVDD1 + 0.05 V
AVDD1
V
+0.12
±5
±10
+10
µA/V
nA/V/°C
nA/V/°C
nA
pA/°C
nA/°C
dB
V
% of V
ppm/°C
ppm/°C
mA
dB
ppm/mA
Rev. B | Page 4 of 60
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| Information | Total 30 Pages | |
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