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AD7606-6 데이터시트 PDF




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기능 8-/6-/4-Channel DAS
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AD7606-6 데이터시트, 핀배열, 회로
Data Sheet
8-/6-/4-Channel DAS with 16-Bit, Bipolar
Input, Simultaneous Sampling ADC
AD7606/AD7606-6/AD7606-4
FEATURES
8/6/4 simultaneously sampled inputs
True bipolar analog input ranges: ±10 V, ±5 V
Single 5 V analog supply and 2.3 V to 5 V VDRIVE
Fully integrated data acquisition solution
Analog input clamp protection
Input buffer with 1 MΩ analog input impedance
Second-order antialiasing analog filter
On-chip accurate reference and reference buffer
16-bit ADC with 200 kSPS on all channels
Oversampling capability with digital filter
Flexible parallel/serial interface
SPI/QSPI™/MICROWIRE™/DSP compatible
Performance
7 kV ESD rating on analog input channels
95.5 dB SNR, −107 dB THD
±0.5 LSB INL, ±0.5 LSB DNL
Low power: 100 mW
Standby mode: 25 mW
64-lead LQFP package
APPLICATIONS
Power-line monitoring and protection systems
Multiphase motor control
Instrumentation and control systems
Multiaxis positioning systems
Data acquisition systems (DAS)
Table 1. High Resolution, Bipolar Input, Simultaneous
Sampling DAS Solutions
Resolution
Single-
Ended
Inputs
True
Differential
Inputs
Number of
Simultaneous
Sampling Channels
18 Bits
AD7608 AD7609
8
16 Bits
AD7606
8
AD7606-6
6
AD7606-4
4
14 Bits
AD7607
8
V1
V1GND
V2
V2GND
V3
V3GND
V4
V4GND
V5
V5GND
V6
V6GND
V7
V7GND
V8
V8GND
CLAMP 1MΩ
CLAMP
1MΩ
1MΩ
CLAMP
CLAMP
1MΩ
1MΩ
CLAMP
CLAMP
1MΩ
1MΩ
CLAMP
CLAMP
1MΩ
CLAMP 1MΩ
CLAMP
1MΩ
1MΩ
CLAMP
CLAMP
1MΩ
1MΩ
CLAMP
CLAMP
1MΩ
1MΩ
CLAMP
CLAMP
1MΩ
FUNCTIONAL BLOCK DIAGRAM
AVCC
AVCC
REGCAP REGCAP REFCAPB REFCAPA
RFB
RFB
SECOND-
ORDER LPF
T/H
RFB
RFB
SECOND-
ORDER LPF
T/H
RFB
RFB
SECOND-
ORDER LPF
T/H
RFB
RFB
SECOND-
ORDER LPF
T/H
RFB
RFB
SECOND-
ORDER LPF
T/H
RFB
RFB
SECOND-
ORDER LPF
T/H
RFB
RFB
SECOND-
ORDER LPF
T/H
RFB
RFB
SECOND-
ORDER LPF
T/H
2.5V
LDO
2.5V
LDO
2.5V
REF
8:1
MUX
16-BIT
SAR
SERIAL
DIGITAL
FILTER
PARALLEL/
SERIAL
INTERFACE
AD7606
CLK OSC
CONTROL
INPUTS
PARALLEL
AGND
CONVST A CONVST B RESET RANGE
Figure 1.
REFIN/REFOUT
REF SELECT
AGND
OS 2
OS 1
OS 0
DOUTA
DOUTB
RD/SCLK
CS
PAR/SER/BYTE SEL
VDRIVE
DB[15:0]
BUSY
FRSTDATA
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2010–2012 Analog Devices, Inc. All rights reserved.




AD7606-6 pdf, 반도체, 판매, 대치품
AD7606/AD7606-6/AD7606-4
Data Sheet
SPECIFICATIONS
VREF = 2.5 V external/internal, AVCC = 4.75 V to 5.25 V, VDRIVE = 2.3 V to 5.25 V, fSAMPLE = 200 kSPS, TA = TMIN to TMAX, unless otherwise noted.1
Table 2.
Parameter
DYNAMIC PERFORMANCE
Signal-to-Noise Ratio (SNR)2, 3
Signal-to-(Noise + Distortion) (SINAD)2
Dynamic Range
Total Harmonic Distortion (THD)2
Peak Harmonic or Spurious Noise (SFDR)2
Intermodulation Distortion (IMD)2
Second-Order Terms
Third-Order Terms
Channel-to-Channel Isolation2
ANALOG INPUT FILTER
Full Power Bandwidth
tGROUP DELAY
DC ACCURACY
Resolution
Differential Nonlinearity2
Integral Nonlinearity2
Total Unadjusted Error (TUE)
Positive Full-Scale Error2, 5
Positive Full-Scale Error Drift
Positive Full-Scale Error Matching2
Bipolar Zero Code Error2, 6
Bipolar Zero Code Error Drift
Bipolar Zero Code Error Matching2
Negative Full-Scale Error2, 5
Negative Full-Scale Error Drift
Negative Full-Scale Error Matching2
Test Conditions/Comments
fIN = 1 kHz sine wave unless otherwise noted
Oversampling by 16; ±10 V range; fIN = 130 Hz
Oversampling by 16; ±5 V range; fIN = 130 Hz
No oversampling; ±10 V Range
No oversampling; ±5 V range
No oversampling; ±10 V range
No oversampling; ±5 V range
No oversampling; ±10 V range
No oversampling; ±5 V range
fa = 1 kHz, fb = 1.1 kHz
fIN on unselected channels up to 160 kHz
−3 dB, ±10 V range
−3 dB, ±5 V range
−0.1 dB, ±10 V range
−0.1 dB, ±5 V range
±10 V Range
±5 V Range
No missing codes
±10 V range
±5 V range
External reference
Internal reference
External reference
Internal reference
±10 V range
±5 V range
±10 V range
± 5 V range
±10 V range
± 5 V range
±10 V range
±5 V range
External reference
Internal reference
External reference
Internal reference
±10 V range
±5 V range
Min
94
93
88.5
87.5
88
87
16
Typ
95.5
94.5
90
89
90
89
90.5
90
−107
−108
−110
−106
−95
23
15
10
5
11
15
Max
−95
±0.5 ±0.99
±0.5 ±2
±6
±12
±8 ±32
±8
±2
±7
5 32
16 40
±1 ±6
±3 ±12
10
5
18
6 22
±8 ±32
±8
±4
±8
5 32
16 40
Unit
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
kHz
kHz
kHz
kHz
µs
µs
Bits
LSB4
LSB
LSB
LSB
LSB
LSB
ppm/°C
ppm/°C
LSB
LSB
LSB
LSB
µV/°C
µV/°C
LSB
LSB
LSB
LSB
ppm/°C
ppm/°C
LSB
LSB
Rev. C | Page 4 of 36

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AD7606-6 전자부품, 판매, 대치품
Data Sheet
AD7606/AD7606-6/AD7606-4
TIMING SPECIFICATIONS
AVCC = 4.75 V to 5.25 V, VDRIVE = 2.3 V to 5.25 V, VREF = 2.5 V external reference/internal reference, TA = TMIN to TMAX, unless otherwise noted.1
Table 3.
Parameter
PARALLEL/SERIAL/BYTE MODE
tCYCLE
tCONV2
tWAKE-UP STANDBY
tWAKE-UP SHUTDOWN
Internal Reference
External Reference
tRESET
tOS_SETUP
tOS_HOLD
t1
t2
t3
t4
t53
t6
t7
PARALLEL/BYTE READ
OPERATION
t8
t9
t10
t11
t12
Limit at TMIN, TMAX
(0.1 × VDRIVE and
0.9 × VDRIVE
Logic Input Levels)
Min Typ Max
5
9.7
3.45
7.87
16.05
33
66
133
257
4
3
2
4.15
9.1
18.8
39
78
158
315
100
30
13
50
20
20
40
25
25
0
0.5
25
25
0
0
16
21
25
32
15
22
Limit at TMIN, TMAX
(0.3 × VDRIVE and
0.7 × VDRIVE
Logic Input Levels)
Min Typ Max
Unit
Description
3.45
7.87
16.05
33
66
133
257
4
3
2
5 µs
9.4 µs
10.7 µs
4.15 µs
µs
µs
9.1 µs
18.8 µs
39 µs
78 µs
158 µs
315 µs
100 µs
1/throughput rate
Parallel mode, reading during or after conversion; or
serial mode: VDRIVE = 3.3 V to 5.25 V, reading during a
conversion using DOUTA and DOUTB lines
Serial mode reading after a conversion; VDRIVE = 2.7 V
Serial mode reading after a conversion; VDRIVE = 2.3 V,
DOUTA and DOUTB lines
Conversion time
Oversampling off; AD7606
Oversampling off; AD7606-6
Oversampling off; AD7606-4
Oversampling by 2; AD7606
Oversampling by 4; AD7606
Oversampling by 8; AD7606
Oversampling by 16; AD7606
Oversampling by 32; AD7606
Oversampling by 64; AD7606
STBY rising edge to CONVST x rising edge; power-up
time from standby mode
30 ms STBY rising edge to CONVST x rising edge; power-up
time from shutdown mode
13 ms STBY rising edge to CONVST x rising edge; power-up
time from shutdown mode
50 ns RESET high pulse width
20 ns BUSY to OS x pin setup time
20 ns BUSY to OS x pin hold time
45 ns
CONVST x high to BUSY high
25 ns Minimum CONVST x low pulse
25 ns Minimum CONVST x high pulse
0 ns BUSY falling edge to CS falling edge setup time
0.5 ms
Maximum delay allowed between CONVST A, CONVST
B rising edges
25 ns
Maximum time between last CS rising edge and BUSY
falling edge
25 ns Minimum delay between RESET low to CONVST x high
0 ns CS to RD setup time
0 ns CS to RD hold time
RD low pulse width
19 ns VDRIVE above 4.75 V
24 ns VDRIVE above 3.3 V
30 ns VDRIVE above 2.7 V
37 ns VDRIVE above 2.3 V
15 ns RD high pulse width
22 ns CS high pulse width (see Figure 5); CS and RD linked
Rev. C | Page 7 of 36

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