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PDF AS29F040 Data sheet ( Hoja de datos )
| Número de pieza | AS29F040 | |
| Descripción | 512K x 8 FLASH | |
| Fabricantes | Micross | |
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Hay una vista previa y un enlace de descarga de AS29F040 (archivo pdf) en la parte inferior de esta página. Total 27 Páginas | ||
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512K x 8 FLASH
UNIFORM SECTOR 5.0V FLASH
MEMORY
AVAILABLE AS MILITARY
SPECIFICATIONS
• MIL-STD-883
• SMD 5962-96692
FEATURES
• Single 5.0V ±10% power supply operation
• Fastest access times: 55, 60, 70, 90, 120, & 150ns
• Low power consumption:
3 20 mA typical active read current
3 30 mA typical program/erase current
3 1 μA typical standby current (standard access time to
active mode)
• Flexible sector architecture
3 Eight uniform 64 Kbyte each
3 Any combination of sectors can be erased
3 Supports full chip erase
• Sector protection
• Embedded Algorithms Erase & Program Algorithms
• Erase Suspend/Resume
• Minimum 1,000,000 Program/Erase Cycles per sector
guaranteed
• Compatible with JEDEC standards
3 Pinout and software compatible with single-power-
supply FLASH
• Data\ Polling and Toggle Bits
• 20-year data retention at 125°C
FLASH
AS29F040
PIN ASSIGNMENT
(Top View)
32-PIN Ceramic DIP (CW)
32-pin Flatpack (F)
32-pin Lead Formed Flatpack (DCG)
A18 1
A16 2
A15 3
A12 4
A7 5
A6 6
A5 7
A4 8
A3 9
A2 10
A1 11
A0 12
DQ0 13
DQ1 14
DQ2 15
VSS 16
32 VCC
31 WE\
30 A17
29 A14
28 A13
27 A8
26 A9
25 A11
24 OE\
23 A10
22 CE\
21 DQ7
20 DQ6
19 DQ5
18 DQ4
17 DQ3
32-PAD Ceramic LCC (ECA)
4 3 2 32 31 30
A7 5
1 29
A6 6
28
A5 7
27
A4 8
26
A3 9
25
A2 10
24
A1 11
23
A0 12
22
I/O0 1134 15 16 17 18 19 2021
A14
A13
A8
A9
A11
OE\
A10
CE\
I/O 7
OPTIONS
• Timing
55ns
60ns
70ns
90ns
120ns
150ns
MARKING
-55
-60
-70
-90
-120
-150
For more products and information
please visit our web site at
www.micross.com
AS29F040
Rev. 2.3 01/10
OPTIONS
• Package Type
Ceramic DIP (600 mil)
Flatpack
Lead Formed Flatpack
Leadless Chip Carrier
MARKING
CW
F
DCG
ECA
• Temperature Ranges
Industrial Temperature (-40°C to +85°C)
Military Temperature (-55°C to +125°C)
883C Processing (-55°C to +125°C)
QML Processing (-55°C to +125°C)
IT
XT**
883C
Q
Micross Components reserves the right to change products or specifications without notice.
1
1 page  
FLASH
AS29F040
When the system is not reading or writing to the device, it
can place the device in the standby mode. In this mode, current
consumption is greatly reduced, and the outputs are placed in
the high impedance state, independent of the OE\ input.
The device enters the CMOS standby mode when the CE\
pin is held at VCC ± 0.5V. (Note that this is a more restricted
vmooldtaegwe hraenngCeEt\hiasnhVeldIHa.)t
The device enters the TTL standby
VIH. The device requires the standard
access
If
ttihmeed(etCvEic)ebeisfodreesiet liescrteeaddydutorinregaderdaastuar.e
or
program-
ming, the device draws active current until the operation is
completed.
curreInCtC3spinecthifiecDatCioCn.haracteristics table represents the standby
Output Disable Mode
When the
disabled. The
OE\ input is at
output pins are
VpIlHac, eodutipnutthferohmightheimdpeevdicaencies
state.
Autoselect Mode
The autoselect mode provides manufacturer and device
identification, and sector protection verification, through
identifier codes output on DQ7 - DQ0. This mode is primarily
intended for programming equipment to automatically match a
device to be programmed with its corresponding programming
algorithm. However, the autoselect codes can also be accessed
in-system through the command register.
When using programming equipment, the autoselect mode
Are6q,uAir1e,saVnIdDA(101m.5uVsttobe1a2s.5shVo)wonn
address pin A9. Address pins
in the Autoselect Codes (High
Voltage Method) table. In addition, when verifying sector
protection, the sector address must appear on the appropriate
highest order address bits. Refer to the
corresponding
Sector Address Tables. The Command Definitions table
shows the remaining address bits that are don’t care. When
all necessary bits have been set as required, the programming
equipment may then read the corresponding identifier code on
DQ7 - DQ0
To access the autoselect codes in-system, the host system
can issue the autoselect command via the command register, as
shown in the Command Definitions table. This method does
nuositnrgeqthueiraeuVtoIsDe.lecSteme o“Cdeo.mmand Definitions” for details on
Sector Protection/Unprotection
The hardware sector protection feature disables both
program and erase operations in any sector. The hardware
sector unprotection feature re-enables both program and erase
operations in previously protected sectors.
Sector protection/unprotection must be implemented us-
ing programming equipment. The procedure requires a high
vdeovltiacgeeis(VshIDip) poend
address
with all
pin A9
sectors
and the control
unprotected. It
pins. The
is possible
to determine whether a sector is protected or unprotected. See
“Autoselect Mode” for details.
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection against
inadvertent writes (refer to the Command Definitions table).
In addition, the following hardware data protection measures
prevent accidental erasure or programming, which might
otherwise be caused by spurious system level signals during
VnoCiCsep. ower-up and power-down transitions, or from system
Low VCC Write Inhibit
When VCC is less than VLKO, the device does not accept
any write cycles. This protects data during VCC power-up and
TABLE 2: SECTOR ADDRESSES TABLE
SECTOR A18 A17 A16 ADDRESS RANGE
SA0 0 0 0 00000h - 0FFFFh
SA1 0 0 1 10000h - 1FFFFh
SA2 0 1 0 20000h - 2FFFFh
SA3 0 1 1 30000h - 3FFFFh
SA4 1 0 0 40000h - 4FFFFh
SA5 1 0 1 50000h - 5FFFFh
SA6 1 1 0 60000h - 6FFFFh
SA7 1 1 1 70000h - 7FFFFh
NOTE: All sectors are 64 Kbytes in size.
AS29F040
Rev. 2.3 01/10
Micross Components reserves the right to change products or specifications without notice.
5
5 Page 
FLASH
AS29F040
toggle. (The system may use either OE\ or CE\ to control
the read cycles.) When the operation is complete, DQ6 stops
toggling.
After an erase command sequence is written, if all sec-
tors selected for erasing are protected, DQ6 toggles for
approximately 100μs, then returns to reading array data. If
not all selected sectors are protected, the Embedded Erase
algorithm erases the unprotected sectors, and ignores the
selected sectors that are protected.
The system can use DQ6 and DQ2 together to determine
whether a sector is actively erasing or is erase-suspended.
When the device is actively erasing (that is, the Embedded
Erase algorithm is in progress), DQ6 toggles. When the device
enters the Erase Suspend mode, DQ6 stops toggling. However
the system must also use DQ2 to determine which sectors are
erasing or erase-suspended. Alternatively, the system can use
DQ7 (see the subsection on “DQ7: Data\ Polling”).
If a program address falls within a protected sector, DQ6
toggles for approximately 2μs after the program command
sequence is written, then returns to reading array data.
DQ6 also toggles during the erase-suspend-program mode,
and stops toggling once the Embedded Program algorithm is
complete.
The Write Operation Status table shows the outputs for
Toggle Bit I on DQ6. Refer to Figure 4 for the toggle bit
algorithm, and to the Toggle Bit Timings figure in the “AC
Characteristics” section for the timing diagram. The DQ2
vs. DQ6 figure shows the differences between DQ2 and DQ6
in graphical form. See also the subsection on “DQ2: Toggle
Bit II”.
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, in-
dicates whether a particular sector is actively erasing (that is,
the Embedded Erase algorithm is in progress), or whether that
sector is erase-suspended. Toggle Bit II is valid after the rising
edge of the final WE\ pulse in the command sequence.
DQ2 toggles when the system reads at addresses within
those sectors taht have been selected for erasure. (The system
may use either OE\ or CE\ to control the read cycles.) But DQ2
cannot distinguish whether the sector is actively erasing or is
erase-suspended. DQ6, by comparison, indicates whether the
device is actively erasing, or is in Erase Suspend, but cannot
distinguish which sectors are selected for erasure. Thus, both
status bits are required for sector and mode information. Refer
to Table 5 to compare outputs for DQ2 and DQ6.
Figure 4 shows the toggle bit algorithm in flowchart form,
and the section “DQ2: Toggle Bit II” explains the algorithm.
See also the “DQ6: Toggle Bit I” subsection. Refer to the
Toggle Bit Timings figure for the toggle bit timing diagram.
The DQ2 vs. DQ6 figure shows the differences between DQ2
and DQ6 in graphical form.
Reading Toggle Bit DQ6/DQ2
Refer to Figure 4 for the following discussion. Whenever
the system initially begins reading toggle bit status, it must
read DQ7-DQ0 at least twice in a row to determine whether a
toggle bit is toggling. Typically, a system would note and store
the value of the toggle bit after the first read. After the second
read, the system would compare the new value of the toggle
bit with the first. If the toggle bit is not toggling, the device
FIGURE 4: TOGGLE BIT ALGORITHM
NOTE:
1) Read toggle bit twice to determine whether or not it is toggling. See text.
2) Recheck toggle bit because it may stop toggling as DQ5 changes to “1”.
See text.
AS29F040
Rev. 2.3 01/10
11
Micross Components reserves the right to change products or specifications without notice.
11 Page | ||
| Páginas | Total 27 Páginas | |
| PDF Descargar | [ Datasheet AS29F040.PDF ] | |
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