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PDF AS4DDR232M64PBG Data sheet ( Hoja de datos )
| Número de pieza | AS4DDR232M64PBG | |
| Descripción | 32M x 64 DDR2 SDRAM | |
| Fabricantes | Micross | |
| Logotipo |  |
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iPEM
2.1 Gb SDRAM-DDR2
AS4DDR232M64PBG
32Mx64 DDR2 SDRAM
iNTEGRATED Plastic Encapsulated Microcircuit
FEATURES
DDR2 Data rate = 667, 533, 400
Available in Industrial, Enhanced and Military Temp
Package:
• 255 Plastic Ball Grid Array (PBGA), 25 x 32mm
• 1.27mm pitch
Differential data strobe (DQS, DQS#) per byte
Internal, pipelined, double data rate architecture
4-bit prefetch architecture
DLL for alignment of DQ and DQS transitions with
clock signal
Four internal banks for concurrent operation
(Per DDR2 SDRAM Die)
Programmable Burst lengths: 4 or 8
Auto Refresh and Self Refresh Modes
On Die Termination (ODT)
Adjustable data – output drive strength
1.8V ±0.1V power supply and I/O (VCC/VCCQ)
Programmable CAS latency: 3, 4, 5, or 6
Posted CAS additive latency: 0, 1, 2, 3 or 4
Write latency = Read latency - 1* tCK
Organized as 32M x 64
Weight: AS4DDR232M64PBG ~ 3.5 grams typical
NOTE: Self Refresh Mode available on Industrial and Enhanced temp. only
BENEFITS
SPACE conscious PBGA defined for easy
SMT manufacturability (50 mil ball pitch)
Reduced part count
47% I/O reduction vs Individual CSP approach
Reduced trace lengths for lower parasitic
capacitance
Suitable for hi-reliability applications
Upgradable to 64M x 64 density
(consult factory for info on
AS4DDR264M64PBG)
ConfigurationAddressing
Parameter
Configuration
RefreshCount
RowAddress
BankAddress
ColumnAddress
32Megx72
8Megx16x4Banks
8K
8K(A0ͲA12)
4(BA0ͲBA1)
1K(A0ͲA9)
FUNCTIONAL BLOCK DIAGRAM
Ax, BA0-2
ODT
VRef
VCC
VCCQ
VSS
VSSQ
VCCL
VSSDL
CS0\
CS1\
CS2\
CS3\
UDMx, LDMx
UDSQx,UDSQx\
LDSQx, LDSQx\
RASx\,CASx\,WEx\
CKx,CKx\,CKEx
A
2
2
2
3
3
VCCL
VSSDL
A2
2
2
3
3
DQ0-15 B
VCCL
VSSDL
B2
2
2
3
3
DQ16-31 C
VCCL
VSSDL
C2
2
2
3
3
DQ32-47
D
AS4DDR232M64PBG
Rev. 1.4 01/10
Micross Components reserves the right to change products or specifications without notice.
1
1 page  
iPEM
2.1 Gb SDRAM-DDR2
AS4DDR232M64PBG
following two sets of conditions (A or B) must be met to
obtain a stable supply state (stable supply defi ned as
V , V , V , and V are between their
CC CCQ REF
TT
minimum and maximum values as stated in Table20);
A. (single power source) The VCC voltage ramp from
300mV to VCC (MIN) must take no longer than
200ms; during the VCC voltage ramp, |VCC - VCCQ|
± 0.3V. Once supply voltage ramping is complete
( w h e n V CCQ c r o s s e s V CC ( M I N ) ) , Ta b l e 2 0
specifications apply.
• V , V are driven from a single power
CC CCQ
converter
output
• VTT is limited to 0.95V MAX
• VREF tracks VCCQ/2; VREF must be within
± 0.3V with respect to VCCQ/2 during supply ramp
time
• VCCQ > VREF at all times
B. (multiple power sources) VCC > VCCQ must be
maintained during supply voltage ramping, for both
AC and DC levels, until supply voltage ramping
completes (VCCQ crosses VCC [MIN]). Once supply
voltage ramping is complete, Table 20 specifications
apply.
• Apply VCC before or at the same time as
VCCQ; VCC voltage ramp time must be < 200ms
from when VCC ramps from 300mV to VCC (MIN)
• Apply VCCQ before or at the same time as VTT; the
VCCQ voltage ramp time from when VCC (MIN) is
achieved to when VCCQ (MIN) is achieved must be
<500ms; while VCC is ramping, current can be
supplied from VCC through the device to VCCQ
• VREF must track VCCQ/2, VREF must be within
± 0.3V with respect to VCCQ/2 during supply ramp
time; VCCQ > VREF must be met at all times
• Apply VTT; The VTT voltage ramp time from when
VCCQ (MIN) is achieved to when VTT(MIN) is achieved
must be no greater than 500ms
2. For a minimum of 200 μs after stable power nd clock
(CK, CK#), apply NOP or DESELECT commands and
take CKE HIGH.
3. Wa i t a m i n i m u m o f 4 0 0 n s , t h e n i s s u e a
PRECHARGE ALL command.
4. Issue an LOAD MODE command to the EMR(2). (To
issue an EMR(2) command, provide LOW to BA0,
provide HIGH to BA1.)
5. Issue a LOAD MODE command to the EMR(3). (To
issue an EMR(3) command, provide HIGH to BA0 and
BA1.)
6. Issue an LOAD MODE command to the EMR to enable
DLL. To issue a DLL ENABLE command, provide LOW
to BA1 and A0, provide HIGH to BA0. Bits E7, E8, and
E9 can be set to “0” or “1”; Micron recommends setting
them to “0”.
7. Issue a LOAD MODE command for DLL RESET. 200
cycles of clock input is required to lock the DLL. (To
issue a DLL RESET, provide HIGH to A8 and provide
LOW to BA1, and BA0.) CKE must be HIGH the entire
time.
8. Issue PRECHARGE ALL command.
9. Issue two or more REFRESH commands, followed
by a dummy WRITE.
AS4DDR232M64PBG
Rev. 1.4 01/10
Micross Components reserves the right to change products or specifications without notice.
5
5 Page 
iPEM
2.1 Gb SDRAM-DDR2
AS4DDR232M64PBG
EXTENDED MODE REGISTER (EMR)
The extended mode register controls functions beyond those
controlled by the mode register; these additional functions are
DLL enable/disable, output drive strength, on die termination
(ODT) (RTT), posted AL, off-chip driver impedance calibration
(OCD), DQS# enable/disable, RDQS/RDQS# enable/disable,
and output disable/enable. These functions are controlled via the
bits shown in Figure 7. The EMR is programmed via the LOAD
MODE (LM) command and will retain the stored information
until it is programmed again or the device loses power.
Reprogramming the EMR will not alter the contents of the memory
array, provided it is performed correctly.
The EMR must be loaded when all banks are idle and no bursts
are in progress, and the controller must wait the specified time
tMRD before initiating any subsequent operation. Violating either
of these requirements could esult in unspecified operation.
FIGURE 7 – EXTENDED MODE REGISTER DEFINITION
BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MRS 02 out RDQS DQS# OCD Program Rtt Posted CAS# Rtt ODS DLL
Extended Mode
Register (Ex)
E12 Outputs
0 Enabled
1 Disabled
E11 RDQS Enable
0 No
1 Yes
E6 E2 Rtt (nominal)
0 0 Rtt Disabled
0 1 75Ω
1 0 150Ω
1 1 50Ω
E0 DLL Enable
0 Enable (Normal)
1 Disable (Test/Debug)
E1 Output Drive Strength
0 Full Strength (18 Ω target)
1 Reduced Strength (40 Ω target)
E10 DQS# Enable
0 Enable
1 Disable
E9 E8 E7 OCD Operation
0 0 0 OCD Not Supported 1
0 0 1 Reserved
0 1 0 Reserved
1 0 0 Reserved
1 1 1 OCD default state 1
E5 E4 E3 Poste d CAS# Add itive Laten cy (AL)
000
0
001
1
010
2
011
3
100
4
101
Reserved
110
Reserved
111
Reserved
E15 E14
Mo de Register Set
00
Mode Register Set (MR S)
0 1 Extended Mode Register (EMR S)
1 0 Extended Mode Register (EMR S2)
1 1 Extended Mode Register (EMR S3)
Note: 1. During initialization, all three bits must be set to "1" for OCD default state,
then must be set to "0" before initialization is finished, as detailed in the
initialization procedure.
2.. E13 (A13) is not used on this device.
AS4DDR232M64PBG
Rev. 1.4 01/10
11
Micross Components reserves the right to change products or specifications without notice.
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet AS4DDR232M64PBG.PDF ] | |
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