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PDF AS4SD32M16 Data sheet ( Hoja de datos )
| Número de pieza | AS4SD32M16 | |
| Descripción | 512Mb: 32 Meg x 16 SDRAM | |
| Fabricantes | Austin Semiconductor | |
| Logotipo |  |
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Austin Semiconductor, Inc.
SDRAM
AS4SD32M16
512Mb: 32 Meg x 16 SDRAM
Synchronous DRAM Memory
FEATURES
• Full Military temp (-55°C to 125°C) processing available
• Configuration: 32 Meg x 16 (8 Meg x 16 x 4 banks)
• Fully synchronous; all signals registered on positive
edge of system clock
• Internal pipelined operation; column address can be
changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8 or full page
• Auto Precharge, includes CONCURRENT AUTO
PRECHARGE and Auto Refresh Modes
• Self Refresh Mode (IT)
• 64ms, 8,192-cycle refresh (IT)
• <24ms 8,192 cycle refresh (XT)
• WRITE Recovery (tWR= “2 CLK”)
• LVTTL-compatible inputs and outputs
• Single +3.3V ±0.3V power supply
PIN ASSIGNMENT
(Top View)
54-Pin TSOP
OPTIONS
• Plastic Package - OCPL*
Copper Lead-Frame (Cu)
MARKING
DGC
• Timing (Cycle Time)
7.5ns @ CL = 3 (PC133) or
7.5ns @ CL = 2 (PC100)
-75
• Operating Temperature Ranges
-Industrial Temp (-40°C to 85° C) IT
-Industrial Plus Temp (-45°C to +105°C) ET
-Military Temp (-55°C to 125°C)
XT
32 Meg x 16
Configuration
8 Meg x 16 x 4 banks
Refresh Count
8K
Row Addressing
8K (A0-A12)
Bank Addressing
4 (BA0, BA1)
Column Addressing
1024 (A0-A9)
Note: “\” indicates an active low.
KEY TIMING PARAMETERS
SPEED
GRADE
-75
-75
CLOCK
ACCESS TIME
FREQUENCY CL = 2** CL = 3**
133 MHz
– 5.4ns
100 MHz
6ns
–
*Off-center parting line
**CL = CAS (READ) latency
SETUP
TIME
1.5ns
1.5ns
HOLD
TIME
0.8ns
0.8ns
For more products and information
please visit our web site at
www.austinsemiconductor.com
AS4SD32M16
Rev. 1.1 3/08
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1
1 page  
Austin Semiconductor, Inc.
SDRAM
AS4SD32M16
FIGURE 1: Mode Register Definition TABLE 1: Burst Definition
BURST STARTING ORDER OF ACCESSES WITHIN A BURST
LENGTH COLUMN TYPE = SEQUENTIAL TYPE = INTERLEAVED
A0
2 0 0-1
0-1
1 1-0
1-0
A1 A0
00
0-1-2-3
0-1-2-3
4
01
1-2-3-0
1-0-3-2
10
2-3-0-1
2-3-0-1
11
3-0-1-2
3-2-1-0
A2 A1 A0
0 0 0 0-1-2-3-4-5-6-7
0-1-2-3-4-5-6-7
0 0 1 1-2-3-4-5-6-7-0
1-0-3-2-5-4-7-6
0 1 0 2-3-4-5-6-7-0-1-
2-3-0-1-6-7-4-5
8 0 1 1 3-4-5-6-7-0-1-2
3-2-1-0-7-6-5-4
1 0 0 4-5-6-7-0-1-2-3
4-5-6-7-0-1-2-3
1 0 1 5-6-7-0-1-2-3-4
5-4-7-6-1-0-3-2
1 1 0 6-7-0-1-2-3-4-5
6-7-4-5-2-3-0-1
1 1 1 7-0-1-2-3-4-5-6
7-6-5-4-3-2-1-0
Full
Page
(y)
Cn, Cn+1, Cn+2, Cn+3,
n=A0-A8
Cn+4…
(location 0-y)
…Cn-1,
Cn…
Not Supported
NOTES:
1. For full-page access: y=512
2. For a burst length of two, A1-A8 select the block-of-two burst;
A0 selects the starting column within the block.
3. For a burst length of four, A2-A8 select the block-of-four burst;
A0-A1 selects the starting column within the block.
4. For a burst length of eight, A3-A8 select the block-of-eight burst;
A0-A2 selects the starting column within the block.
5. For a full-page burst, the full row is selected and A0-A8 select the
starting column.
6. Whenever a boundary of the block is reached within a given
sequence above, the following access wraps within the block.
7. For a burst length of one, A0-A8 select the unique column to be
accessed, and mode register bit M3 is ignored.
AS4SD32M16
Rev. 1.1 3/08
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5
5 Page 
Austin Semiconductor, Inc.
FIGURE 7: Consecutive READ Bursts
SDRAM
AS4SD32M16
AS4SD32M16
Rev. 1.1 3/08
11
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AS4SD32M16.PDF ] | |
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