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PDF AS4SD8M16 Data sheet ( Hoja de datos )

Número de pieza AS4SD8M16
Descripción 128 Mb: 8 Meg x 16 SDRAM
Fabricantes Austin Semiconductor 
Logotipo Austin Semiconductor Logotipo



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No Preview Available ! AS4SD8M16 Hoja de datos, Descripción, Manual

Austin Semiconductor, Inc.
SDRAM
AS4SD8M16
128 Mb: 8 Meg x 16 SDRAM
Synchronous DRAM Memory
FEATURES
• Full Military temp (-55°C to 125°C) processing avail-
able
• Configuration: 8 Meg x 16 (2 Meg x 16 x 4 banks)
• Fully synchronous; all signals registered on positive
edge of system clock
• Internal pipelined operation; column address can be
changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8 or full page
• Auto Precharge, includes CONCURRENT AUTO
PRECHARGE and Auto Refresh Modes
• Self Refresh Mode (IT)
• 64ms, 4,096-cycle refresh (IT)
• <24ms 4,096 cycle recfresh (XT)
• WRITE Recovery (tWR = “2 CLK”)
• LVTTL-compatible inputs and outputs
• Single +3.3V ±0.3V power supply
OPTIONS
• Plastic Package - OCPL*
54-pin TSOP (400 mil)
MARKING
DG No. 901
Timing (Cycle Time)
7.5ns @ CL = 3 (PC133) or
7.5ns @ CL = 2 (PC100)
-75
Operating Temperature Ranges
-Industrial Temp (-40°C to 85° C) IT
-Industrial Plus Temp (-45°C to +105°C) ET
-Military Temp (-55°C to 125°C)
XT***
PIN ASSIGNMENT
(Top View)
54-Pin TSOP
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
VDD
DQML
WE\
CAS\
RAS\
CS\
BA0
BA1
A10
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54 VSS
53 DQ15
52 VSSQ
51 DQ14
50 DQ13
49 VDDQ
48 DQ12
47 DQ11
46 VSSQ
45 DQ10
44 DQ9
43 VDDQ
42 DQ8
41 VSS
40 NC
39 DQMH
38 CLK
37 CKE
36 NC
35 A11
34 A9
33 A8
32 A7
31 A6
30 A5
29 A4
28 Vss
KEY TIMING PARAMETERS
SPEED
GRADE
-75
-75
CLOCK
ACCESS TIME
FREQUENCY CL = 2** CL = 3**
133 MHz
– 5.4ns
100 MHz
6ns
*Off-center parting line
**CL = CAS (READ) latency
***Consult Factory
SETUP
TIME
1.5ns
1.5ns
AS4SD8M16
Rev. 0.5 04/05
HOLD
TIME
0.8ns
0.8ns
8 Meg x 16
Configuration
2 Meg x 16 x 4 banks
Refresh Count
4K
Row Addressing
4K (A0-A11)
Bank Addressing
4 (BA0, BA1)
Column Addressing
512 (A0-A8)
Note: “\” indicates an active low.
For more products and information
please visit our web site at
www.austinsemiconductor.com
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1

1 page




AS4SD8M16 pdf
Austin Semiconductor, Inc.
SDRAM
AS4SD8M16
FIGURE 1: Mode Register Definition
TABLE 1: Burst Definition
BURST STARTING ORDER OF ACCESSES WITHIN A BURST
LENGTH COLUMN TYPE = SEQUENTIAL TYPE = INTERLEAVED
A0
2 0 0-1
0-1
1 1-0
1-0
A1 A0
00
0-1-2-3
0-1-2-3
4
01
1-2-3-0
1-0-3-2
10
2-3-0-1
2-3-0-1
11
3-0-1-2
3-2-1-0
A2 A1 A0
0 0 0 0-1-2-3-4-5-6-7
0-1-2-3-4-5-6-7
0 0 1 1-2-3-4-5-6-7-0
1-0-3-2-5-4-7-6
0 1 0 2-3-4-5-6-7-0-1-
2-3-0-1-6-7-4-5
8 0 1 1 3-4-5-6-7-0-1-2
3-2-1-0-7-6-5-4
1 0 0 4-5-6-7-0-1-2-3
4-5-6-7-0-1-2-3
1 0 1 5-6-7-0-1-2-3-4
5-4-7-6-1-0-3-2
1 1 0 6-7-0-1-2-3-4-5
6-7-4-5-2-3-0-1
1 1 1 7-0-1-2-3-4-5-6
7-6-5-4-3-2-1-0
Full
Page
(y)
Cn, Cn+1, Cn+2, Cn+3,
n=A0-A8
Cn+4…
(location 0-y)
…Cn-1,
Cn…
Not Supported
NOTES:
1. For full-page access: y=512
2. For a burst length of two, A1-A8 select the block-of-two burst;
A0 selects the starting column within the block.
3. For a burst length of four, A2-A8 select the block-of-four burst;
A0-A1 selects the starting column within the block.
4. For a burst length of eight, A3-A8 select the block-of-eight burst; A0-A2
selects the starting column within the block.
5. For a full-page burst, the full row is selected and A0-A8 select the starting
column.
6. Whenever a boundary of the block is reached within a given sequence
above, the following access wraps within the block.
7. For a burst length of one, A0-A8 select the unique column to be accessed,
and mode register bit M3 is ignored.
AS4SD8M16
Rev. 0.5 04/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5

5 Page





AS4SD8M16 arduino
Austin Semiconductor, Inc.
FIGURE 7: Consecutive READ Bursts
SDRAM
AS4SD8M16
AS4SD8M16
Rev. 0.5 04/05
11
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

11 Page







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