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AS4SD8M16 데이터시트 PDF




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기능 128 Mb: 8 Meg x 16 SDRAM
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AS4SD8M16 데이터시트, 핀배열, 회로
SDRAM
AS4SD8M16
128 Mb: 8 Meg x 16 SDRAM
Synchronous DRAM Memory
FEATURES
• Full Military temp (-55°C to 125°C) processing available
• Configuration: 8 Meg x 16 (2 Meg x 16 x 4 banks)
• Fully synchronous; all signals registered on positive
edge of system clock
• Internal pipelined operation; column address can be
changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8 or full page
• Auto Precharge, includes CONCURRENT AUTO
PRECHARGE and Auto Refresh Modes
• Self Refresh Mode (IT & ET)
• 64ms, 4,096-cycle refresh (IT)
• 24ms 4,096 cycle recfresh (XT)
• WRITE Recovery (tWR = “2 CLK”)
• LVTTL-compatible inputs and outputs
• Single +3.3V ±0.3V power supply
OPTIONS
Plastic Package
54-pin TSOPII (400 mil)
(Pb/Sn finish or RoHS available)
MARKING
DG No. 901
Timing (Cycle Time)
7.5ns @ CL = 3 (PC133) or
10ns @ CL = 2 (PC100)
-75
Operating Temperature Ranges
-Industrial Temp (-40°C to 85° C)
-Enhanced Temp (-40°C to +105°C)
-Military Temp (-55°C to 125°C)
IT
ET
XT
KEY TIMING PARAMETERS
SPEED CLOCK
ACCESS TIME
GRADE FREQUENCY CL = 2** CL = 3**
-75 133 MHz
– 5.4ns
-75 100 MHz 6ns
*Off-center parting line
**CL = CAS (READ) latency
SETUP
TIME
1.5ns
1.5ns
HOLD
TIME
0.8ns
0.8ns
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
VDD
DQML
WE\
CAS\
RAS\
CS\
BA0
BA1
A10
A0
A1
A2
A3
VDD
PIN ASSIGNMENT
(Top View)
54-Pin TSOP
1 54
2 53
3 52
4 51
5 50
6 49
7 48
8 47
9 46
10 45
11 44
12 43
13 42
14 41
15 40
16 39
17 38
18 37
19 36
20 35
21 34
22 33
23 32
24 31
25 30
26 29
27 28
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
VSS
NC
DQMH
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
Vss
Package may or may not be
assembled with a location notch.
8 Meg x 16
Configuration
2 Meg x 16 x 4 banks
Refresh Count
4K
Row Addressing
4K (A0-A11)
Bank Addressing
4 (BA0, BA1)
Column Addressing
512 (A0-A8)
Note: “\” indicates an active low.
For more products and information
please visit our web site at www.micross.com
AS4SD8M16
Rev. 1.6 March 27, 2015
Micross Components reserves the right to change products or specifications without notice.
1




AS4SD8M16 pdf, 반도체, 판매, 대치품
SDRAM
AS4SD8M16
FUNCTIONAL DESCRIPTION
In general, the 128Mb SDRAMs are quad-bank DRAMs
that operate at 3.3V and include a synchronous interface (all
signals are registered on the positive edge of the clock signal,
CLK). Each of the 33,554,432-bit banks is organized as 4,096
rows by 512 columns by 16 bits.
Read and write accesses to the SDRAM are burst ori-
ented; accesses start at a selected location and continue for a
programmed number of locations in a programmed sequence.
Accesses begin with the registration of an ACTIVE command,
which is then followed by a READ or WRITE command. The
address bits registered coincident with the ACTIVE command
are used to select the bank and row to be accessed (BA0 and
BA1 select the bank, A0 - A11 select the row). The address
bits (A0 - A8) registered coincident with the READ or WRITE
command are used to select the starting column location for the
burst access.
Prior to normal operation, the SDRAM must be initialized.
The following sections provide detailed information covering
device initialization, register definition, command descriptions
and device operation.
Initialization
SDRAMs must be powered up and initialized in a pre-
defined manner. Operational procedures other than those
specified may result in undefined operation. Once power is
applied to VDD and VDDQ (simultaneously) and the clock is
stable (stable clock is defined as a signal cycling within timing
constraints specified for the clock pin), the SDRAM requires a
100µs delay prior to issuing any command other than a COM-
MAND INHIBIT or NOP. Starting at some point during
this 100µs period and continuing at least through the end of
this period, COMMAND INHIBIT or NOP commands should
be applied.
Once the 100µs delay has been satisfied with at least one
COMMAND INHIBIT or NOP command having been applied,
a PRECHARGE command should be applied. All banks must
then be precharged, thereby placing the device in the all banks
idle state.
Once in the idle state, two AUTO REFRESH cycles must
be preformed. After the AUTO REFRESH cycles are complete,
the SDRAM is ready for mode register programming. Because
the mode register will power up in an unknown state, it should
be loaded prior to applying any operational command.
Register Definition
MODE REGISTER
The mode register is used to define the specific mode
of operation of the SDRAM. This definition includes the
selection of a burst length, a burst type, a CAS latency, an
operating mode and a write burst mode, as shown in Figure
1. The mode register is programmed via the LOAD MODE
REGISTER command and will retain the stored information
until it is programmed again or the device loses power.
Mode register bits M0 - M2 specify the burst length, M3
specifies the type of burst (sequential or interleaved), M4 - M6
specify the CAS latency, M7 and M8 specify the operating
mode, M9 specifies the write burst mode, and M10 and M11
are reserved for future use.
The mode register must be loaded when all banks are
idle, and the controller must wait the specified time before
initiating the subsequent operation. Violating either of these
requirements will result in unspecified operation.
Burst Length
Read and write accesses to the SDRAM are burst oriented,
with the burst length being programmable, as shown in Fig-
ure 1. The burst length determines the maximum number of
column locations that can be accessed for a given READ or
WRITE command. Burst lengths of 1, 2, 4, or 8 locations are
available for both the sequential and the interleaved burst types,
and a full-page burst is available for the sequential types. The
full-page burst is used in conjunction with the BURST
TERMINATE command to generate arbitrary burst lengths.
Reserved states should not be used as unknown
operation or incompatibility with future versions may result.
When a READ or WRITE command is issued, a block of
columns equal to the burst length is effectively selected. All
accesses for that burst take place within this block, meaning that
the burst will wrap within the block if a boundary is reached.
The clock is uniquely selected by A1-A8 when the burst length
is set to two; by A2-A8 when the burst length is set to four, and
by A3-A8 when the burst length is set to eight. The remain-
ing (least significant) address bit(s) is (are) used to select the
starting location within the block. Full-page bursts wrap within
the page if the boundary is reached.
Burst Type
Accesses within a given burst may be programmed to be
either sequential or interleaved; this is referred to as the burst
type and is selected via bit M3.
The ordering of accesses within a burst is determined
by the burst length, the burst type and the starting column
address, shown in table 1.
AS4SD8M16
Rev. 1.6 March 27, 2015
Micross Components reserves the right to change products or specifications without notice.
4

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AS4SD8M16 전자부품, 판매, 대치품
SDRAM
AS4SD8M16
COMMANDS
Truth Table 1 provides a quick reference of available
commands. This is followed by a written description of each
command. Three additional Truth Tables appear following the
Operation section; these tables provide current state/next state
information.
COMMAND INHIBIT
The COMMAND INHIBIT function prevents new
commands from being executed by the SDRAM, regardless of
whether the CLK signal is enabled. The SDRAM is effectively
deselected. Operations already in progress are not affected.
NO OPERATION (NOP)
The NO OPERATION (NOP) command is used to per-
form a NOP to an SDRAM which is selected (CS\ is LOW).
This prevents unwanted commands from being registered
during idle or wait states. Operations already in progress are
not affected.
LOAD MODE REGISTER
The mode register is loaded via inputs A0-A11. See mode
register heading in the Register Definition section. The LOAD
MODE REGISTER command can only be issued when all
banks are idle, and a subsequent executable command cannot be
issued until tMRD is met.
ACTIVE
The ACTIVE command is used to open (or activate) a row
in a particular bank for a subsequent access. The value on the
BA0, BA1 inputs selects the bank, and the address provided
on inputs A0-A11 selects the row. The row remains active (or
open) for accesses until a PRECHARGE command is issued to
that bank. A PRECHARGE command must be issued before
opening a different row in the same bank.
READ
The READ command is used to initiate a burst read access
to an active row. The value on the BA0, BA1 inputs selects
the bank, and the address provided on inputs A0-A8 selects the
starting column location. The value on input A10 determines
whether or not auto precharge is used. If auto precharge is
selected, the row being accessed will be precharged at the end
of the READ burst; if auto precharge is not selected, the row
will remain open for subsequent accesses. Read data appears
on the DQs subject to the logic level on the DQM inputs two
clocks earlier. If a given DQM signal was registered HIGH,
the corresponding DQs will be High-Z two clocks later; if the
DQM signal was registered LOW, the DQs will provide valid
data.
WRITE
The WRITE command is used to initiate a burst write
access to an active row. The value on the BA0, BA1 inputs
TRUTH TABLE 1: COMMANDS AND DQM OPERATION1
FUNCTION
COMMAND INHIBIT (NOP)
NO OPERATION (NOP)
ACTIVE (Select bank and activate row)
CS\ RAS\ CAS\ WE\ DQM ADDR DQs NOTES
HX X X X X X
LH H H X X X
L L H H X Bank/Row X
3
READ (Select bank and column, and start READ burst)
L H L H L/H8 Bank/Col X
4
WRITE (Select bank and column, and start WRITE burst) L H L L L/H8 Bank/Col Valid 4
BURST TERMINATE
LH H L X
X Active
PRECHARGE (Deactivate row in bank or banks)
LL H L X
Code
X
5
AUTO REFRESH or SELF REFRESH
(Enter self refresh mode)
L L L H X X X 6, 7
LOAD MODE REGISTER
L L L L X Op-Code X
2
Write Enable/Output Enable
-- - - L
- Active 8
Write Inhibit/Output High-Z
-- - - H
- High-Z 8
NOTE:
1. CKE is HIGH for all commands shown except SELF REFRESH.
2. A0-A11 define the op-code written to the mode register.
3. A0-A11 provide row address, and BA0, BA1 determine which bank is made active.
4. A0-A8 provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), while A10 LOW disables the auto precharge
BA0, BA1 determine which bank is being read from or written to.
5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged and BA0, BA1 are “Don’t Care.”
6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
8. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay).
feature;
AS4SD8M16
Rev. 1.6 March 27, 2015
Micross Components reserves the right to change products or specifications without notice.
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AS4SD8M16

128 Mb: 8 Meg x 16 SDRAM

Micross
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AS4SD8M16

128 Mb: 8 Meg x 16 SDRAM

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