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AS5SP128K36 데이터시트 PDF




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기능 Synchronous SRAM
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AS5SP128K36 데이터시트, 핀배열, 회로
Plastic Encapsulated Microcircuit
4.5Mb, 128K x 36, Synchronous SRAM
Pipeline Burst, Single Cycle Deselect
FEATURES
• Synchronous Operation in relation to the input Clock
• 2 Stage Registers resulting in Pipeline operation
• On chip address counter (base +3) for Burst operations
• Self-Timed Write Cycles
• On-Chip Address and Control Registers
• Byte Write support
• Global Write support
• On-Chip low power mode [powerdown] via ZZ pin
• Interleaved or Linear Burst support via Mode pin
• Three Chip Enables for ease of depth expansion without
Data Contention.
• Two Cycle load, Single Cycle Deselect
• Asynchronous Output Enable (OE\)
• Three Pin Burst Control (ADSP\, ADSC\, ADV\)
• 3.3V Core Power Supply
• 3.3V/2.5V IO Power Supply
• JEDEC Standard 100 pin TQFP Package
• Available in Industrial, Enhanced, and Mil-Temperature
Operating Ranges
RoHs compliant options available
DQPc
DQc
DQc
VDDQ
VSSQ
DQc
DQc
DQc
DQc
VSSQ
VDDQ
DQc
DQc
NC
VDD
NC
VSS
DQd
DQd
VDDQ
VSSQ
DQd
DQd
DQd
DQd
VSSQ
VDDQ
DQd
DQd
DQPd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
SSRAM
AS5SP128K36
SSRAM [SPB]
80 DQPb
79 DQb
78 DQb
77 VDDQ
76 VSSQ
75 DQb
74 DQb
73 DQb
72 DQb
71 VSSQ
70 VDDQ
69 DQb
68 DQb
67 VSS
66 NC
65 VDD
64 ZZ
63 DQa
62 DQa
61 VDDQ
60 VSSQ
59 DQa
58 DQa
57 DQa
56 DQa
55 VSSQ
54 VDDQ
53 DQa
52 DQa
51 DQPa
FAST ACCESS TIMES
Parameter
Cycle Time
Clock Access Time
Output Enable Access Time
Symbol
tCYC
tCD
tOE
200Mhz
5.0
3.0
3.0
166Mhz
6.0
3.5
3.5
BLOCK DIAGRAM
OE\
ZZ
CLK
CE1\
CE2
CE3\
BWE\
BWx\
GW\
ADV
ADSC\
ADSP\
MODE
A0-Ax
CONTROL
BLOCK
BURST CNTL.
Address
Registers
Row
Decode
Column
Decode
I/O Gating and Control
Memory Array
x36
SBP
Synchronous Pipeline
Burst
Two (2) cycle load
One (1) cycle
de-select
One (1) cycle latency
on Mode change
133Mhz
7.5
4.0
4.0
Units
ns
ns
ns
GENERAL DESCRIPTION
The AS5SP128K36 is a 4.5Mb High Performance Synchronous
Pipeline Burst SRAM, available in multiple temperature
screening levels, fabricated using High Performance CMOS
technology and is organized as a 128K x 36. It integrates
address and control registers, a two (2) bit burst address
counter supporting four (4) double-word transfers. Writes are
internally self-timed and synchronous to the rising edge of
clock.
Output Output
Register Driver
Input
Register
The AS5SP128K36 includes advanced control options
including Global Write, Byte Write as well as an Asynchronous
Output enable. Burst Cycle controls are handled by three (3)
input pins, ADV, ADSP\ and ADSC\. Burst operation can be
initiated with either the Address Status Processor (ADSP\) or
DQx, DQPx Address Status Cache controller (ADSC\) inputs. Subsequent
burst addresses are generated internally in the system’s burst
sequence control block and are controlled by Address Advance
(ADV) control input.
AS5SP128K36
Rev. 1.6 10/13
Micross Components reserves the right to change products or specications without notice.
1




AS5SP128K36 pdf, 반도체, 판매, 대치품
SSRAM
AS5SP128K36
Functional Description
Micross Components AAS5SP128K36 Synchronous SRAM is
manufactured to support today’s High Performance platforms
utilizing the Industries leading Processor elements including
those of Intel and Motorola. The AS5SP128K36 supports Syn-
chronous SRAM READ and WRITE operations as well as Syn-
chronous Burst READ/WRITE operations. All inputs with the
exception of OE\, MODE and ZZ are synchronous in nature
and sampled and registered on the rising edge of the devices
input clock (CLK). The type, start and the duration of Burst
Mode operations is controlled by MODE, ADSC\, ADSP\ and
ADV as well as the Chip Enable pins CE1\, CE2, and CE3\.
All synchronous accesses including the Burst accesses are
enabled via the use of the multiple enable pins and wait state
insertion is supported and controlled via the use of the Ad-
vance control (ADV).
TheAS5SP128K36 supports both Interleaved as well as Linear
Burst modes therefore making it an architectural t for either
the Intel or Motorola CISC processor elements available on
the Market today.
The AS5SP128K36 supports Byte WRITE operations and
enters this functional mode with the Byte Write Enable (BWE\)
and the Byte Write Select pin(s) (BWa\, BWb\, BWc\, BWd\).
Global Writes are supported via the Global Write Enable (GW\)
and Global Write Enable will override the Byte Write inputs and
will perform a Write to all Data I/Os.
The AS5SP128K36 provides ease of producing very dense
arrays via the multiple Chip Enable input pins and Tri-state
outputs.
Single Cycle Access Operations
A Single READ operation is initiated when all of the following
conditions are satised at the time of Clock (CLK) HIGH: [1]
ADSP\ pr ADSC\ is asserted LOW, [2] Chip Enables are all
asserted active, and [3] the WRITE signals (GW\, BWE\) are in
their FALSE state (HIGH). ADSP\ is ignored if CE1\ is HIGH.
The address presented to the Address inputs is stored within
the Address Registers and Address Counter/Advancement
Logic and then passed or presented to the array core. The
corresponding data of the addressed location is propagated to
the Output Registers and passed to the data bus on the next
rising clock via the Output Buffers. The time at which the data
is presented to the Data bus is as specied by either the Clock
to Data valid specication or the Output Enable to Data Valid
spec for the device speed grade chosen. The only exception
occurs when the device is recovering from a deselected to se-
lect state where its outputs are tristated in the rst machine
cycle and controlled by its Output Enable (OE\) on following
cycle. Consecutive single cycle READS are supported. Once
the READ operation has been completed and deselected by
use of the Chip Enable(s) and either ADSP\ or ADSC\, its out-
puts will tri-state immediately.
A Single ADSP\ controlled WRITE operation is initiated when
both of the following conditions are satised at the time of
Clock (CLK) HIGH: [1] ADSP\ is asserted LOW, and [2] Chip
Enable(s) are asserted ACTIVE. The address presented to the
address bus is registered and loaded on CLK HIGH, then pre-
sented to the core array. The WRITE controls Global Write,
and Byte Write Enable (GW\, BWE\) as well as the individual
Byte Writes (BWa\, BWb\, BWc\, and BWd\) and ADV\ are ig-
nored on the rst machine cycle. ADSP\ triggered WRITE ac-
cesses require two (2) machine cycles to complete. If Global
Write is asserted LOW on the second Clock (CLK) rise, the
data presented to the array via the Data bus will be written
into the array at the corresponding address location specied
by the Address bus. If GW\ is HIGH (inactive) then BWE\ and
one or more of the Byte Write controls (BWa\, BWb\, BWc\ and
BWd\) controls the write operation. All WRITES that are initi-
ated in this device are internally self timed.
A Single ADSC\ controlled WRITE operation is initiated when
the following conditions are satised: [1] ADSC\ is asserted
LOW, [2] ADSP\ is de-asserted (HIGH), [3] Chip Enable(s) are
asserted (TRUE or Active), and [4] the appropriate combina-
tion of the WRITE inputs (GW\, BWE\, BWx\) are asserted
(ACTIVE). Thus completing the WRITE to the desired Byte(s)
or the complete data-path. ADSC\ triggered WRITE accesses
require a single clock (CLK) machine cycle to complete. The
address presented to the input Address bus pins at time of
clock HIGH will be the location that the WRITE occurs. The
ADV pin is ignored during this cycle, and the data WRITTEN to
the array will either be a BYTE WRITE or a GLOBAL WRITE
depending on the use of the WRITE control functions GW\ and
BWE\ as well as the individual BYTE CONTOLS (BWx\).
Deep Power-Down Mode (SLEEP)
The AS5SP128K36 has a Deep Power-Down mode and is
controlled by the ZZ pin. The ZZ pin is an Asynchronous input
and asserting this pin places the SSRAM in a deep power-
down mode (SLEEP). White in this mode, Data integrity is
guaranteed. For the device to be placed successfully into this
operational mode the device must be deselected and the Chip
Enables, ADSP\ and ADSC\ remain inactive for the duration
of tZZREC after the ZZ input returns LOW. Use of this deep
power-down mode conserves power and is very useful in mul-
tiple memory page designs where the mode recovery time can
be hidden.
AS5SP128K36
Rev. 1.6 10/13
Micross Components reserves the right to change products or specications without notice.
4

4페이지










AS5SP128K36 전자부품, 판매, 대치품
SSRAM
AS5SP128K36
AC SWITCHING CHARACTERISTICS (VDD=3.3V -5%/+10%,
TA= MIN. AND MAX TEMPERATURES OF SCREENING LEVEL CHOSEN)
Parameter
Clock (CLK) Cycle Time
Clock (CLK) High Time
Clock (CLK) Low Time
Clock Access Time
Clock (CLK) High to Output Low-Z
Clock High to Output High-Z
Output Enable to Data Valid
Output Hold from Clock High
Output Enable Low to Output Low-Z
Output Enable High to Output High-Z
Address Set-up to CLK High
Address Hold from CLK High
Address Status Set-up to CLK High
Address Status Hold from CLK High
Address Advance Set-up to CLK High
Address Advance Hold from CLK High
Chip Enable Set-up to CLK High (CEx\, CE2)
Chip Enable Hold from CLK High (CEx\, CE2)
Data Set-up to CLK High
Data Hold from CLK High
Write Set-up to CLK High (GW\, BWE\, BWx\)
Write Hold from CLK High (GW\, BWE\, BWX\)
ZZ High to Power Down
ZZ Low to Power Up
Symbol
tCYC
tCH
tCL
tCD
tCLZ
tCHZ
tOE
tOH
tOELZ
tOEHZ
tAS
tAH
tASS
tASH
tADVS
tADVH
tCES
tCEH
tDS
tDH
tWES
tWEH
tPD
tPU
-5 [200Mhz]
Min.
Max.
5.00
-
2.00
-
2.00
-
3.00
1.00
-
1.00 3.00
- 3.00
1.00
-
0.00
-
- 3.00
1.40
0.40
1.40
0.40
1.40
0.40
1.40
0.40
1.40
0.40
1.40
0.40
2
2
-6 [166Mhz]
Min.
Max.
6.00
-
2.50
-
2.50
-
3.50
1.00
-
1.00 3.50
- 3.50
1.00
-
0.00
-
- 3.50
1.50
0.50
1.50
0.50
1.50
0.50
1.50
0.50
1.50
0.50
1.50
0.50
2
2
-7.5 [133Mhz]
Min.
Max.
7.50
-
3.00
-
3.00
-
4.00
1.00
-
1.00 3.50
- 4.00
1.00
-
0.00
-
- 3.50
1.50
0.50
1.50
0.50
1.50
0.50
1.50
0.50
1.50
0.50
1.50
0.50
2
2
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
cycles
cycles
Notes
1
1
2
2,3,4,5
2,3,4,5
6
2,3,4,5
2,3,4,5
7,8
7,8
7,8
7,8
7,8
7,8
7,8
7,8
7,8
7,8
7,8
7,8
Notes to Switching Specications:
1. Measured as HIGH when above VIH and Low when below VIL
2. This parameter is measured with the output loading shown in AC Test Loads
3. This parameter is sampled
4. Transition is measured +500mV from steady state voltage
5. Critical specication(s) when Design Considerations are being reviewed/analyized for Bus Contentention
6. OE\ is a Don't Care when a Byte or Global Write is sampled LOW
7. A READ cycle is dened by Byte or Global Writes sampled LOW and ADSP\ is sampled HIGH for the required
SET-UP and HOLD times
8. This is a Synchronous device. All addresses must meet the specied SET-UP and HOLD times for all rising
edges of CLK when either ADSP\ or ADSC\ is sampled LOW while the device is enabled. All other synchronous
inputs must meet the SET-UP and HOLD times with stable logic levels for all rising edges of clock (CLK) during
device operation (enabled). Chip Enable (Cex\, CE2) must be valid at each rising edge of clock (CLK) when
either ADSP\ or ADSC\ is LOW to remain enabled.
AS5SP128K36
Rev. 1.6 10/13
Micross Components reserves the right to change products or specications without notice.
7

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