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AS5SP512K18 데이터시트 PDF




Micross에서 제조한 전자 부품 AS5SP512K18은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

PDF 형식의 AS5SP512K18 자료 제공

부품번호 AS5SP512K18 기능
기능 Synchronous SRAM
제조업체 Micross
로고 Micross 로고


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AS5SP512K18 데이터시트, 핀배열, 회로
Plastic Encapsulated Microcircuit
9Mb, 512K x 18, Synchronous SRAM
Pipeline Burst, Single Cycle Deselect
FEATURES
 Synchronous Operation in relation to the input Clock
 2 Stage Registers resulting in Pipeline operation
 On chip address counter for Burst operations
 Self-Timed Write Cycles
 On-Chip Address and Control Registers
 Byte Write support
 Global Write support
 On-Chip low power mode [powerdown] via ZZ pin
 Interleaved or Linear Burst support via Mode pin
 Three Chip Enables for ease of depth expansion
without Data Contention.
 Two Cycle load, Single Cycle Deselect
 Asynchronous Output Enable (OE\)
 Three Pin Burst Control (ADSP\, ADSC\, ADV\)
 3.3V Core Power Supply
 3.3V/2.5V IO Power Supply
 JEDEC Standard 100 pin TQFP Package
 Available in Industrial (-40oC to +85oC), Enhanced
(-40oC to +105oC), and Mil-Temperature (-55oC to
+125oC) Operating Ranges
 RoHS compliant options
NC
NC
NC
VDDQ
VSSQ
NC
NC
DQb
DQb
VSSQ
VDDQ
DQb
DQb
NC
VDD
NC
VSS
DQb
DQb
VDDQ
VSSQ
DQb
DQb
DQPb
NC
VSSQ
VDDQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
SSRAM
AS5SP512K18
SSRAM [SPB]
80 A
79 NC
78 NC
77 VDDQ
76 VSSQ
75 NC
74 DQPa
73 DQa
72 DQa
71 VSSQ
70 VDDQ
69 DQa
68 DQa
67 VSS
66 NC
65 VDD
64 ZZ
63 DQa
62 DQa
61 VDDQ
60 VSSQ
59 DQa
58 DQa
57 NC
56 NC
55 VSSQ
54 VDDQ
53 NC
52 NC
51 NC
FAST ACCESS TIMES
Parameter
Symbol
Cycle Time
tCYC
Clock Access Time
tCD
Output Enable Access tOE
200Mhz
5.0
3.0
3.0
166Mhz
6.0
3.5
3.5
133Mhz
7.5
4.0
4.0
Units
ns
ns
ns
BLOCK DIAGRAM
OE\
ZZ
CLK
CE1\
CE2
CE3\
BWE\
BWx\
GW\
ADV\
ADSC\
ADSP\
MODE
A0-Ax
CONTROL
BLOCK
BURST CNTL.
Address
Registers
Row
Decode
Column
Decode
I/O Gating and Control
Memory Array
x18
SBP
T Synchronous Pipeline
Burst
N Two (2) cycle load
N One (1) cycle
de-select
N One (1) cycle latency
on Mode change
Output Output
Register Driver
Input
Register
AS5SP512K18
Rev. 2.4 10/13
DQx, DQPx
1
GENERAL DESCRIPTION
Micross Components AS5SP512K18 is a 9.0Mb High
Performance Synchronous Pipeline Burst SRAM, available
in multiple temperature screening levels, fabricated using
High Performance CMOS technology and is organized as
a 512K x 18. It integrates address and control registers,
a two (2) bit burst address counter supporting four (4)
double-word transfers. Writes are internally self-timed and
synchronous to the rising edge of clock.
The AS5SP512K18 includes advanced control options
including Global Write, Byte Write as well as an
Asynchronous Output enable. Burst Cycle controls
are handled by three (3) input pins, ADV\, ADSP\ and
ADSC\. Burst operation can be initiated with either the
Address Status Processor (ADSP\) or Address Status Cache
controller (ADSC\) inputs. Subsequent burst addresses are
generated internally in the system’s burst sequence control
block and are controlled by Address Advance (ADV\)
control input.
Micross Components reserves the right to change products or specications without notice.




AS5SP512K18 pdf, 반도체, 판매, 대치품
SSRAM
AS5SP512K18
DEEP POWER-DOWN MODE (SLEEP)
The AS5SP512K18 has a Deep Power-Down mode and is controlled by the ZZ pin. The ZZ pin is an Asynchronous input and
asserting this pin places the SSRAM in a deep power-down mode (SLEEP). While in this mode, Data integrity is guaranteed.
For the device to be placed successfully into this operational mode the device must be deselected and the Chip Enables, ADSP\
and ADSC\ remain inactive for the duration of tZZREC after the ZZ input returns LOW. Use of this deep power-down mode
conserves power and is very useful in multiple memory page designs where the mode recovery time can be hidden. Accesses
pending when entering sleep mode are not considered valid and completion of the operation is not guaranteed.
SYNCHRONOUS TRUTH TABLES
CE1\
H
L
L
L
L
L
L
L
X
H
X
H
X
H
X
H
Notes:
CE2
CE3\
ADSP\ ADSC\
ADV\ WT / RD
XXXLXX
LXLXXX
XH L XXX
L XH L XX
XHHL XX
HL LXXX
H L H L X WT
H L H L X RD
X X H H L RD
X X X H L RD
X X H H L WT
X X X H L WT
X X H H H RD
X X X H H RD
X X H H H WT
X X X H H WT
1. X = Don’t Care
2. WT= WRITE operation in WRITE TABLE, RD= READ operation in WRITE TABLE
BURST SEQUENCE TABLES
CLK
Address Accessed
Operation
NA Not Selected
NA Not Selected
NA Not Selected
NA Not Selected
NA Not Selected
External Address Begin Burst, READ
External Address Begin Burst, WRITE
External Address Begin Burst, READ
Next Address Continue Burst, READ
Next Address Continue Burst, READ
Next Address Continue Burst, WRITE
Next Address Continue Burst, WRITE
Current Address Suspend Burst, READ
Current Address Suspend Burst, READ
Current Address Suspend Burst, WRITE
Current Address Suspend Burst, WRITE
CAPACITANCE
Burst Control State
Pin [MODE] HIGH
First Address
Fourth Address
Interleaved Burst
Case 1
Case 2
A1 A0 A1 A0
0001
0100
1011
1110
Case 3
A1 A0
10
11
00
01
Case 4
A1 A0
11
10
01
00
Parameter
Input Capacitance
Input/Output Capacitance
Clock Input Capacitance
Symbol
CI
CIO
CCLK
Max.
6
8
6
Units
pF
pF
pF
Burst Control State
Pin [MODE] LOW
First Address
Fourth Address
Linear Burst
Case 1
A1 A0
Case 2
A1 A0
0001
0110
1011
1100
Case 3
A1 A0
10
11
00
01
Case 4
A1 A0
11
00
01
10
WRITE TABLE
GW\
H
H
H
H
H
L
BW\ BWa\ BWb\
HXX
L HH
L LH
LHL
LLL
XXX
Operation
READ
READ
WRITE Byte [A]
WRITE Byte [B]
WRITE ALL Bytes
WRITE ALL Bytes
ASYNCHRONOUS TRUTH TABLE
Operation
Power-Down (SLEEP)
READ
WRITE
De-Selected
ZZ
H
L
L
L
L
OE\
X
L
H
X
X
I/O Status
High-Z
DQ
High-Z
Din, High-Z
High-Z
AS5SP512K18
Rev. 2.4 10/13
Micross Components reserves the right to change products or specications without notice.
4

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AS5SP512K18 전자부품, 판매, 대치품
SSRAM
AS5SP512K18
AC SWITCHING WAVEFORMS
Write Cycle Timing
Single Write
tCYC
Burst Write
tCH
Pipelined Write
CLK
ADSP\
tASS
tASH
tCL
ADSP\ Ignored with CE1\ inactive
ADSC\
tASS
ADV\
tADVS
Ax
GW\
A1
tAS tAH
tWES
BWE\, BWx\
CE1\
tCES
tCEH
tASH
tADVH ADV\ Must be Inactive for ADSP\ Write
A2 A3
tWEH
tWES
CE1\ Masks ADSP\
tWEH
CE2
CE3\
OE\
DQx,DQPx
DON'T CARE
UNDEFINED
tDS
tDH
W1
W2a W2b
W2c
W2d
W3
AS5SP512K18
Rev. 2.4 10/13
Micross Components reserves the right to change products or specications without notice.
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관련 데이터시트

부품번호상세설명 및 기능제조사
AS5SP512K18

Synchronous SRAM

Micross
Micross
AS5SP512K18DQ

Plastic Encapsulated Microcircuit 9Mb

Austin Semiconductor
Austin Semiconductor

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