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PDF AS5SP512K36 Data sheet ( Hoja de datos )
| Número de pieza | AS5SP512K36 | |
| Descripción | Synchronous SRAM | |
| Fabricantes | Micross | |
| Logotipo |  |
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Plastic Encapsulated Microcircuit
18Mb, 512K x 36, Synchronous SRAM
Pipeline Burst, Single Cycle Deselect
FEATURES
Synchronous Operation in relation to the input Clock
2 Stage Registers resulting in Pipeline operation
On chip address counter (base +3) for Burst operations
Self-Timed Write Cycles
On-Chip Address and Control Registers
Byte Write support
Global Write support
On-Chip low power mode [powerdown] via ZZ pin
Interleaved or Linear Burst support via Mode pin
Three Chip Enables for ease of depth expansion without
Data Contention.
Two Cycle load, Single Cycle Deselect
Asynchronous Output Enable (OE\)
Three Pin Burst Control (ADSP\, ADSC\, ADV\)
3.3V Core Power Supply
3.3V/2.5V IO Power Supply
JEDEC Standard 100 pin TQFP Package
Available in Industrial, Enhanced, and Mil-
Temperature Operating Ranges
RoHs compliant options available
SSRAM
AS5SP512K36
100-PIN TQFP
PINOUT
(3-CHIP ENABLE)
Fast Access Times
Parameter
Cycle Time
Clock Access Time
Output Enable Access Time
Symbol
tCYC
tCD
tOE
200Mhz
5.0
3.1
3.1
166Mhz
6.0
3.5
3.5
133Mhz
7.5
4.0
4.0
Block Diagram
OE\
ZZ
CLK
CE1\
CE2
CE3\
BWE\
BWx\
GW\
ADV\
ADSC\
ADSP\
MODE
A0-Ax
CONTROL
BLOCK
BURST CNTL.
Address
Registers
Row
Decode
Column
Decode
I/O Gating and Control
Memory Array
x36
SBP
❑ Synchronous Pipeline
Burst
❋ Two (2) cycle load
❋ One (1) cycle
de-select
❋ One (1) cycle latency
on Mode change
Output Output
Register Driver
Input
Register
Units
ns
ns
ns
DQx, DQPx
GENERAL DESCRIPTION
The AS5SP512K36 is a 18Mb High Performance
Synchronous Pipeline Burst SRAM, available in multiple
temperature screening levels, fabricated using High
Performance CMOS technology and is organized as a
512K x 36 array. It integrates address and control registers,
a two (2) bit burst address counter supporting four (4)
double-word transfers. Writes are internally self-timed and
synchronous to the rising edge of clock.
The AS5SP512K36 includes advanced control options
including Global Write, Byte Write as well as an
asynchronous output enable. Burst Cycle controls are
handled by three (3) input pins, ADV\, ADSP\ and ADSC\.
Burst operation can be initiated with either the Address
Status Processor (ADSP\) or Address Status controller
(ADSC\) inputs. Subsequent burst addresses are generated
internally in the system’s burst sequence control block and
are controlled by the Address Advance (ADV\) control
input.
AS5SP512K36
Rev. 3.0 10/13
Micross Components reserves the right to change products or specifications without notice.
1
1 page  
SSRAM
AS5SP512K36
DC Electrical Characteristics (VDD = 3.3v ± 5%, VDDQ = 3.3V/2.5V ± 5%, VDDQ ≤ VDD) [1, 2]
TA=Min. and Max temperatures of Screening level chosen
Symbol
VDD
VDDQ
VoH
VoL
VIH
VIL
IIL
IZ
IOL
IDD
ISB1
ISB2
Parameter
Power Supply Voltage
I/O Supply Voltage
Output High Voltage
Output Low Voltage
Input High Voltage
Input Low Voltage
Input Leakage (except ZZ) Mode Pin
Input Leakage, ZZ pin
Output Leakage
Operating Current
Automatic CE, Power Down
Current - TTL inputs
CMOS Standby
Test Conditions
VDD=Min., IOH=-4mA
VDD=Min., IOH=-1mA
VDD=Min., IOL=8mA
VDD=Min., IOL=1mA
VDD=Max., VIN=VSS to VDD
3.3v
2.5v
3.3v
2.5v
3.3v
2.5v
3.3v
2.5v
Output Disabled, VOUT=VSSQ to VDDQ
VDD=Max., f=Max.,
5.0ns Cycle, 200 Mhz
IOH=0mA
6.0ns Cycle, 166 Mhz
7.5ns Cycle, 133 Mhz
Max VDD, De-Selected,
VIN>=VIH or VIN</=VIL
5.0ns Cycle, 200 Mhz
f=1/tCYC
6.0ns Cycle, 166 Mhz
7.5ns Cycle, 133 Mhz
Max. VDD, Device deselected, VIN </=0.3V or VIN>/=VDDQ-0.3V
f=1/tCYC
Min
3.465
2.375
2.4
2
2
1.7
-5
-30
-5
Max
3.630
VDD
0.4
0.4
0.8
0.7
5
30
5
475
425
375
250
225
200
200
Units
V
V
V
V
V
V
V
V
V
V
uA
uA
uA
mA
mA
mA
mA
mA
mA
mA
Notes
4
3
3
Thermal Resistance
Parameter
Description
ȺJA
ThermalResistance
(JunctiontoAmbient)
ȺJC
ThermalResistance
(JunctiontoCase)
TestConditions
Testconditionsfollowstandardtest
methodsandproceduresfor
measuringthermalimpedance,per
EIA/JESD51
DQ DQC
Package Package Unit
28.66 30.2 oC/W
4.08 6.5 oC/W
Notes:
[1]
[2]
[3]
[4]
All Voltages referenced to VSS (Logic Ground)
Overshoot: VIH(AC) < VDD +1.5V (Pulsewidth less than tCYC/2)
Undershoot: VIL(AC) > -2V (Pulsewidth less than tCYCLZ)
tPower-up: Assumes a linear amp from OV to VDD(MIN) within zooms.
During this time VIH VDD and VDDQ VDD
MODE and ZZ pins have internal pull-up resistors
VDDQ should never exceed VDD, VDD and VDDQ can be connected together
AS5SP512K36
Rev. 3.0 10/13
Micross Components reserves the right to change products or specifications without notice.
5
5 Page 
SSRAM
AS5SP512K36
MECHANICAL DEFINITION
100-Pin TQFP (Package Designator DQ)
AS5SP512K36
Rev. 3.0 10/13
11
Micross Components reserves the right to change products or specifications without notice.
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet AS5SP512K36.PDF ] | |
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