PDF AS5SS256K36 Data sheet ( Hoja de datos )

Número de pieza	AS5SS256K36
Descripción	256K x 36 SSRAM
Fabricantes	Micross
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No Preview Available ! 256K x 36 SSRAM Flow-Through, Synchronous Burst SRAM FEATURES  Organized 256K x 36  Fast Clock and OE\ access times  Single +3.3V +0.3V/-0.165V power supply (VDD)  SNOOZE MODE for reduced-power standby  Common data inputs and data outputs  Individual BYTE WRITE control and GLOBAL WRITE  Three chip enables for simple depth expansion and address pipelining  Clock-controlled and registered addresses, data I/Os and control signals  Internally self-timed WRITE cycle  Burst control (interleaved or linear burst)  Automatic power-down for portable applications  Low capacitive bus loading  100-lead TQFP package for high density, high speed  RoHs compliant options available OPTIONS  Timing 7.5ns/8.5ns/117MHz 8.5ns/10ns/100MHz 10ns/15ns/66MHz MARKING -7.5 -8.5 -10  Packages TQFP DQ No. 1001  Operating Temperature Ranges Military (-55oC to +125oC) Enhanced (-40oC to +105oC) Industrial (-40oC to +85oC) /XT /ET /IT GENERAL DESCRIPTION The AS5SS256K36 employs high-speed, low-power CMOS designs that are fabricated using an advanced CMOS process. This 8Mb Synchronous Burst SRAM integrates a 256K x 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. All synchronous inputs pass through registers controlled by a positive-edge-triggered single-clock input (CLK). The synchronous inputs include all addresses, all data inputs, active LOW chip enable (CE\), two additional chip enables for easy depth expansion (CE2\, CE2), burst control inputs (ADSC\, ADSP\, ADV\), byte write enables (BWx\) and global write (GW\). SSRAM AS5SS256K36 PIN ASSIGNMENT (Top View) 100-pin TQFP (DQ) DQPc DQc DQc VDDQ Vss DQc DQc DQc DQc Vss VDDQ DQc DQc Vss VDD NC Vss DQd DQd VDDQ Vss DQd DQd DQd DQd Vss VDDQ DQd DQd DQPd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 DQPb 79 DQb 78 DQb 77 VDDQ 76 Vss 75 DQb 74 DQb 73 DQb 72 DQb 71 Vss 70 VDDQ 69 DQb 68 DQb 67 Vss 66 NC 65 VDD 64 ZZ 63 DQa 62 DQa 61 VDDQ 60 Vss 59 DQa 58 DQa 57 DQa 56 DQa 55 Vss 54 VDDQ 53 DQa 52 DQa 51 DQPa For more products and information please visit our web site at www.micross.com AS5SS256K36 Rev. 4.4 10/13 Micross Components reserves the right to change products or speciﬁcations without notice. 1 1 page SSRAM AS5SS256K36 INTERLEAVED BURST ADDRESS TABLE (MODE = NC OR HIGH) FIRST ADDRESS (EXTERNAL) SECOND ADDRESS (INTERNAL) THIRD ADDRESS (INTERNAL) FOURTH ADDRESS (INTERNAL) X…X00 X…X01 X…X10 X…X11 X…X01 X…X00 X…X11 X…X10 X…X10 X…X11 X…X00 X…X01 X…X11 X…X10 X…X01 X…X00 LINEAR BURST ADDRESS TABLE (MODE = LOW) FIRST ADDRESS (EXTERNAL) SECOND ADDRESS (INTERNAL) THIRD ADDRESS (INTERNAL) FOURTH ADDRESS (INTERNAL) X…X00 X…X01 X…X10 X…X11 X…X01 X…X10 X…X11 X…X00 X…X10 X…X11 X…X00 X…X01 X…X11 X…X00 X…X01 X…X10 PARTIAL TRUTH TABLE FOR WRITE COMMANDS FUNCTION READ READ WRITE Byte "a" WRITE All Bytes WRITE All Bytes GW\ H H H H L BWE\ H L L L X BWa\ X H L L X BWb\ X H H L X BWc\ X H H L X BWd\ X H H L X AS5SS256K36 Rev. 4.4 10/13 Micross Components reserves the right to change products or speciﬁcations without notice. 5 5 Page SSRAM AS5SS256K36 SNOOZE MODE SNOOZE MODE is a low-current, “power-down” mode in which the device is deselected and current is reduced to ISB2Z. The duration of SNOOZE MODE is dictated by the length of time ZZ is in a HIGH state. After the device enters SNOOZE MODE, all inputs except ZZ become gated inputs and are ignored. ZZ is an asynchronous, active HIGH input that causes the device to enter SNOOZE MODE. When ZZ becomes a logic HIGH, ISB2Z is guaranteed after the setup time tZZ is met. Any READ or WRITE operation pending when the device enters SNOOZE MODE is not guaranteed to complete successfully. Therefore, SNOOZE MODE must not be initiated until valid pending operations are completed. SNOOZE MODE ELECTRICAL CHARACTERISTICS DESCRIPTION Current during SNOOZE MODE ZZ active to input ignored ZZ inactive to input sampled ZZ active to snooze current ZZ inactive to exit snooze current NOTE: 1. This parameter is sampled. CONDITIONS ZZ > VIH SYM ISB2Z tZZ tRZZ tZZI tRZZI MIN 2tcyc 0 MAX 80 2tcyc 2tcyc UNITS mA ns ns ns ns NOTES 1 1 1 1 AS5SS256K36 Rev. 4.4 10/13 SNOOZE MODE WAVEFORM CLK ZZ ISUPPLY ALL INPUTS* *Except ZZ t ZZ tZZI tSB2 t RZZ tRZZI Don’t Care 11 Micross Components reserves the right to change products or speciﬁcations without notice. 11 Page

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