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PDF AS8ER128K32 Data sheet ( Hoja de datos )
| Número de pieza | AS8ER128K32 | |
| Descripción | 128K x 32 Radiation Tolerant EEPROM | |
| Fabricantes | Austin Semiconductor | |
| Logotipo |  |
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Austin Semiconductor, Inc.
EEPROM
AS8ER128K32
128K x 32 RadiationTolerant EEPROM
AVAILABLE AS MILITARY SPECIFICATIONS
• MIL-STD-883
• SMD 5962-94585
FEATURES
• Access time of 150ns, 200ns, 250ns
• Operation with single 5V + 10% supply
• Power Dissipation:
Active: 1.43 W (MAX), Max Speed Operation
Standby: 7.7 mW (MAX), Battery Back-up Mode
• Automatic Byte Write: 10 ms (MAX)
• Automatic Page Write (128 bytes): 10 ms (MAX)
• Data protection circuit on power on/off
• Low power CMOS
• 104 Erase/Write cycles (in Page Mode)
• Software data protection
• TTL Compatible Inputs and Outputs
• Data Retention: 10 years
• Ready/Busy\ and Data Polling Signals
• Write protection by RES\ pin
• Radiation Tolerant: Proven total dose 40K to 100K RADS*
• Shielded Package for Best Radiation Immunity
• Operating Temperature Ranges:
Military: -55oC to +125oC
Industrial: -40oC to +85oC
OPTIONS
• Timing
150 ns
200 ns
250 ns
MARKINGS
-150
-200
-250
PIN ASSIGNMENT
(Top View)
68 Lead CQFP
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
GND
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
1 0 6 0 I/O16
1 1 5 9 I/O17
1 2 5 8 I/O18
1 3 5 7 I/O19
1 4 5 6 I/O20
1 5 5 5 I/O21
1 6 5 4 I/O22
1 7 5 3 I/O23
18 52 GND
1 9 5 1 I/O24
2 0 5 0 I/O25
2 1 4 9 I/O26
2 2 4 8 I/O27
2 3 4 7 I/O28
2 4 4 6 I/O29
2 5 4 5 I/O30
2 6 4 4 I/O31
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
*Pin #'s 31 and 32, A15 and A14 respectively, are reversed from the AS8E128K32. Correct
use of these address lines is required for operation of the SDP mode to work properly.
PIN NAME
FUNCTION
A0 to A16 Address Input
I/O0 to I/O31 Data Input/Output
OE\ Output Enable
CE\ Chip Enable
WE\ Write Enable
VCC Power Supply
VSS Ground
RDY/BUSY\ Ready Busy
RES\
Reset
• Package
Ceramic Quad Flat pack w/ formed leads
Ceramic Quad Flat pack w/ tie bar
Shielded Ceramic Quad Flat pack
Shielded Ceramic Quad Flat pack
Q No. 703Q
QB No. 703QB
SQ No. 703SF
SQB No. 703SQB
GENERAL DESCRIPTION
The Austin Semiconductor, Inc. AS8ER128K32 is a 4 Megabit
Radiation Tolerant EEPROM Module organized as 128K x 32 bit.
User configurable to 256K x16 or 512Kx 8. The module achieves high
speed access, low power consumption and high reliability by
employing advanced CMOS memory technology.
The military grade product is manufactured in compliance to
MIL-STD 883, making the AS8ER128K32 ideally suited for military
or space applications.
The module is offered as a 68 lead 0.880 inch square ceramic
quad flat pack. It has a max. height of 0.200 inch (non-shielded). This
package design is targeted for those applications which require low
profile SMT Packaging.
* contact factory for test reports. ASI does not guarantee or warrant
these performance levels, but references these third party reports.
AS8ER128K32
Rev. 5.3 6/05
1
FUNCTIONAL BLOCK DIAGRAM
For more products and information
please visit our web site at
www.austinsemiconductor.com
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1 page  
Austin Semiconductor, Inc.
EEPROM
AS8ER128K32
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC WRITE CHARACTERISTICS
(-55oC < TA < +125oC; Vcc = 5V +10%)
SYMBOL
PARAMETER
MIN(2)
MAX
UNITS
tAS Address Setup Time
0 ms
tAH Address Hold Time
150 ns
tCS CE\ to Write Setup Time (WE\ controlled)
0
ns
tCH CE\ Hold Time (WE\ controlled)
0 ns
tWS WE\ to Write Setup Time (CE\ controlled)
0
ns
tWH WE\ to Hold Time (CE\ controlled)
0 ns
tOES OE\ to Write Setup Time
0 ns
tOEH OE\ to Hold Time
0 ns
tDS Data Setup Time
100 ns
tDH Data Hold Time
10 ns
tWP WE\ Pulse Width (WE\ controlled)
250 ns
tCW CE\ Pulse Width (CE\ controlled)
250 ns
tDL Data Latch Time
300 ns
tBLC Byte Load Cycle
0.55
30
µs
tBL Byte Load Window
tWC Write Cycle Time
100 µs
10 (3)
ms
tDB Time to Device Busy
tDW Write Start Time
120
150 (4)
ns
ns
tRP
tRES
Reset Protect Time
Reset High Time (5)
100 µs
1 µs
ADDRESS
CE\
OE\
WE\
Data Out
RES\
AS8ER128K32
Rev. 5.3 6/05
READ TIMING WAVEFORM
VIH
HIGH-Z
tACC
tCE
tOE
tOH
tDF
DATAOUT VALID
tRR
tDFR
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5
5 Page 
Austin Semiconductor, Inc.
EEPROM
AS8ER128K32
WE\, CE\ Pin Operation
During a write cycle, address are latched by the falling edge
of WE\ or CE\, and data is latched by the rising edge of WE\
or CE\.
Write/Erase Endurance and Data Retention Time
The endurance is 104 cycles in case of the page programming
and 103 cycles in case of the byte programming (1% cumula-
tive failure rate). The data retention time is more than 10
years when a device is page-programmed less than 104 cycles.
RDY/Busy\ SIGNAL
RDY/Busy\ signal also allows status of the EEPROM to
be determined. The RDY/Busy\ signal has high impedance
except in write cycle and is lowered to VOL after the first write
signal. At the end of the write cycle, the RDY/Busy\ signal
changes state to high impedance. This allows many 58C1001
devices RDY/Busy\ signal lines to be wired-OR together.
PROGRAMMING/ERASE
The 58C1001 does NOT employ a BULK-erase function.
The memory cells can be programmed ‘0’ or ‘1’. A write cycle
performs the function of erase & write on every cycle with
the erase being transparent to the user. The internal erase data
state is considered to be ‘1’. To program the memory array
with background of ALL 0’s or All 1’s, the user would
program this data using the page mode write operation to
program all 1024 128-byte pages.
has a noise cancellation function that cuts noise if its width is
20ns or less in program mode.
Be careful not to allow noise of a width more than
20ns on the control pins. See Diagram 1 below.
2. Data Protection at VCC On/Off
When VCC is turned on or off, noise on the control
pins generated by external circuits (CPU, etc.) may act as a
trigger and turn the EEPROM to program mode by mistake.
To prevent this unintentional programming, the EEPROM must
be kept in an unprogrammable state while the CPR is in an
unstable state.
NOTE: The EEPROM should be kept in
unprogrammable state during VCC on/off by using CPU RE-
SET signal. See the timing diagram below.
DIAGRAM 1
Data Protection
1. Data Protection against Noise on Control Pins (CE\,
OE\, WE\) During Operation
During readout or standby, noise on the control pins
may act as a trigger and turn the EEPROM to programming
mode by mistake. To prevent this phenomenon, this device
DATA PROTECTION AT VCC ON/OFF
VCC
CPU
RESET
*Unprogrammable
*Unprogrammable
AS8ER128K32
Rev. 5.3 6/05
11
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet AS8ER128K32.PDF ] | |
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