|
|
PDF AS8ERLC128K32 Data sheet ( Hoja de datos )
| Número de pieza | AS8ERLC128K32 | |
| Descripción | 128K x 32 Radiation Tolerant EEPROM | |
| Fabricantes | Micross | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de AS8ERLC128K32 (archivo pdf) en la parte inferior de esta página. Total 19 Páginas | ||
|
No Preview Available !
EEPROM
AS8ERLC128K32
128K x 32 Radiation Tolerant EEPROM
AVAILABLE AS MILITARY
SPECIFICATIONS
• MIL-PRF-38534
FEATURES
• Access time of 250ns , 300ns
• Operation with single 3.3V (+ .3V) supply
• LOW Power Dissipation:
Active(Worst case): 300mW (MAX), Max Speed Operation
Standby(Worst case): 7.2mW(MAX), Battery Back-up Mode
• Automatic Byte Write: 15 ms (MAX)
• Automatic Page Write (128 bytes): 15 ms (MAX)
• Data protection circuit on power -on/off
• Low power CMOS MNOS cell Technology
• 104 Erase/Write cycles (in Page Mode)
• Software data protection
• TTL Compatible Inputs and Outputs
• Data Retention: 10 years
• Ready/Busy\ and Data Polling Signals
• Write protection by RES\ pin
• Radiation Tolerant: Proven total dose 40K to 100K RADS*
• Shielded Package for Best Radiation Immunity
• Operating Temperature Ranges:
Military: -55oC to +125oC
Industrial: -40oC to +85oC
OPTIONS
• Timing
250 ns
300 ns
MARKINGS
-250
-300
PIN ASSIGNMENT
(Top View)
68 Lead CQFP
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
GND
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
10 60
11 59
12 58
13 57
14 56
15 55
16 54
17 53
18 52
19 51
20 50
21 49
22 48
23 47
24 46
25 45
26 44
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
I/O16
I/O17
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23
GND
I/O24
I/O25
I/O26
I/O27
I/O28
I/O29
I/O30
I/O31
*Pin #'s 31 and 32, A15 and A14 respectively, are reversed from the AS8E128K32. Correct use
of these address lines is required for operation of the SDP mode to work properly.
PIN NAME FFUUNNCCTTIOIONN
A0 to A16 Address Input
I/O0 to I/O31 DataFFInUUpNNutCC/OTTuIItOOpuNNt
OE\ Output Enable
CE\ ChFFipUUENNnCCabTTleIIOONN
WE\ Write Enable
VCC FFPoUUwNNeCCr STTuIIOOppNNly
VRSDSY/BUSYF\FUURGNNeroCaCudTTnydIIBOOuNNsy
RES\
Reset
• Package
Ceramic Quad Flat pack w/ formed leads
Ceramic Quad Flat pack w/ tie bar
Shielded Ceramic Quad Flat pack
Q No. 703Q
QB No. 703QB
SQ No. 703SF
Shielded Ceramic Quad Flat pack
SQB No. 703SQB
GENERAL DESCRIPTION
The AS8ERLC128K32 is a 4 Megabit Radiation Tolerant
EEPROM Module organized as 128K x 32 bit. User configurable to
256K x16 or 512Kx 8. The module achieves high speed access, low
power consumption and high reliability by employing advanced CMOS
memory technology.
The military grade product is manufactured in compliance to MIL-
STD 883, making the AS8ERLC128K32 ideally suited for military or
space applications.
The module is offered as a 68 lead 0.880 inch square ceramic
quad flat pack. It has a max. height of 0.200 inch (non-shielded). This
package design is targeted for those applications which require low
profile SMT Packaging.
* Contact factory for more information. 2-sided shielding provided via Tungsten
lids on both sides. 6.5X typ. TID boost due to shielding. (Geostationary orbit)
Proven total dose 40K to 100K RADS. Micross can perform TID lot testing.
AS8ERLC128K32
Rev. 2.1 11/10
1
RDY/ BUSY\
RES\
FUNCTIONAL BLOCK DIAGRAM
For more products and information
please visit our web site at
www.micross.com
Micross Components reserves the right to change products or specifications without notice.
1 page  
EEPROM
AS8ERLC128K32
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC WRITE CHARACTERISTICS
(-55oC < TA < +125oC; Vcc = 3.3V +.3V)
SYMBOL
PARAMETER
tAS Address Setup Time
tAH Address Hold Time
tCS CE\ to Write Setup Time (WE\ controlled)
tCH CE\ Hold Time (WE\ controlled)
tWS WE\ to Write Setup Time (CE\ controlled)
tWH WE\ to Hold Time (CE\ controlled)
tOES OE\ to Write Setup Time
tOEH OE\ to Hold Time
tDS Data Setup Time
tDH Data Hold Time
tWP WE\ Pulse Width (WE\ controlled)
tCW CE\ Pulse Width (CE\ controlled)
tDL Data Latch Time
tBLC Byte Load Cycle
tBL Byte Load Window
tWC Write Cycle Time
tDB Time to Device Busy
tDW Write Start Time
tRP
tRES
Reset Protect Time
Reset High Time (5)
MIN(2)
0
150
0
0
0
0
0
0
100
10
250
250
750
1
100
150
250 (4)
100
2
MAX
30
15 (3)
UNITS
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
μs
ms
ns
ns
μs
μs
READ TIMING WAVEFORM
ADDRESS
CE\
OE\
WE\
Data Out
RES\
AS8ERLC128K32
Rev. 2.1 11/10
VIH
HIGH-Z
tACC
tCE
tOE
tRR
tOH
tDF
DATA OUT VALID
tDFR
Micross Components reserves the right to change products or specifications without notice.
5
5 Page 
EEPROM
AS8ERLC128K32
WE\, CE\ Pin Operation
During a write cycle, address are latched by the falling edge
of WE\ or CE\, and data is latched by the rising edge of WE\
or CE\.
Write/Erase Endurance and Data Retention Time
The endurance is 104 cycles in case of the page programming
and 103 cycles in case of the byte programming (1% cumulative
failure rate). The data retention time is more than 10 years when
a device is page-programmed less than 104 cycles.
RDY/Busy\ SIGNAL
RDY/Busy\ signal also allows status of the EEPROM to be
determined. The RDY/Busy\ signal has high impedance except
in write cycle
At the end of
and
the
wisrliotewceyrecdlet,othVeORL DafYte/rBtuhseyfi\rssitgwnariltechsaignngaels.
state to high impedance. This allows many AS8ERLC128K32
devices RDY/Busy\ signal lines to be wired-OR together.
mode by mistake. To prevent this phenomenon, this device has
a noise cancellation function that cuts noise if its width is 20ns
or less in program mode.
Be careful not to allow noise of a width more than
20ns on the control pins. See Diagram 1 below.
2. Data Protection at VCC On/Off
generatedWbhyeenxVteCrCnaisl
turned on or off, noise on
circuits (CPU, etc.) may
the
act
control pins
as a trigger
and turn the EEPROM to program mode by mistake. To prevent
this unintentional programming, the EEPROM must be kept
in an unprogrammable state while the CPR is in an unstable
state.
NOTE: The EEPROM should be kept in unprogram-
mSeaebtlheesttaimteindgurdiniaggrVamCC
on/off
below.
by
using
CPU
RESET
signal.
PROGRAMMING/ERASE
The AS8ERLC128K32 does NOT employ a BULK-
erase function. The memory cells can be programmed ‘0’ or
‘1’. A write cycle performs the function of erase & write on
every cycle with the erase being transparent to the user. The
internal erase data state is considered to be ‘1’. To program
the memory array with background of ALL 0’s or All 1’s, the
user would program this data using the page mode write
operation to program all 1024 128-byte pages.
DIAGRAM 1
Data Protection
1. Data Protection against Noise on Control Pins (CE\,
OE\, WE\) During Operation
During readout or standby, noise on the control pins
may act as a trigger and turn the EEPROM to programming
DATA PROTECTION AT VCC ON/OFF
VCC
CPU
RESET
*Unprogrammable
*Unprogrammable
AS8ERLC128K32
Rev. 2.1 11/10
11
Micross Components reserves the right to change products or specifications without notice.
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet AS8ERLC128K32.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| AS8ERLC128K32 | 128K x 32 Radiation Tolerant EEPROM | Micross |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |