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SST25WF512 데이터시트 PDF




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부품번호 SST25WF512 기능
기능 1.8V SPI Serial Flash
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SST25WF512 데이터시트, 핀배열, 회로
Obsolete Device
Please contact Microchip Sales for replacement information.
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit 1.8V SPI Serial Flash
SST25WF512 / SST25WF010 / SST25WF020 / SST25WF040
EOL Data Sheet
SST25WF512 / SST25WF010 / SST25WF020 / SST25WF040 are members of
the Serial Flash 25 Series family and feature a four-wire, SPI-compatible interface
that allows for a low pin-count package which occupies less board space and ulti-
mately lowers total system costs. SPI serial flash memory is manufactured with
SST proprietary, high performance CMOS SuperFlash technology. The split-gate
cell design and thick-oxide tunneling injector attain better reliability and manufac-
turability compared with alternate approaches.
Features
• Single Voltage Read and Write Operations
– 1.65-1.95V
• Serial Interface Architecture
– SPI Compatible: Mode 0 and Mode 3
• High Speed Clock Frequency
– 40MHz
• Superior Reliability
– Endurance: 100,000 Cycles
– Greater than 100 years Data Retention
• Ultra-Low Power Consumption:
– Active Read Current: 2 mA (typical @ 20MHz)
– Standby Current: 2 µA (typical)
• Flexible Erase Capability
– Uniform 4 KByte sectors
– Uniform 32 KByte overlay blocks
– Uniform 64 KByte overlay blocks
(2 Mbit and 4 Mbit only)
• Fast Erase and Byte-Program:
– Chip-Erase Time: 125 ms (typical)
– Sector-/Block-Erase Time: 62ms (typical)
– Byte-Program Time: 50 µS (typical)
• Auto Address Increment (AAI) Programming
– Decrease total chip programming time over Byte-Pro-
gram operations
• End-of-Write Detection
– Software polling the BUSY bit in Status Register
– Busy Status readout on SO pin
• Reset Pin (RST#) or Programmable Hold Pin
(HOLD#) option
– Hardware Reset pin as default
– Hold pin option to suspend a serial sequence without
deselecting the device
• Write Protection (WP#)
– Enables/Disables the Lock-Down function of the status
register
• Software Write Protection
– Write protection through Block-Protection bits in status
register
• Temperature Range
– Industrial: -40°C to +85°C
• Packages Available
– 8-lead SOIC (150 mils)
– 8-contact WSON (5mm x 6mm)
• All devices are RoHS compliant
©2014 Silicon Storage Technology, Inc.
www.microchip.com
DS20005016C
11/14




SST25WF512 pdf, 반도체, 판매, 대치품
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit 1.8V SPI Serial Flash
SST25WF512 / SST25WF010 / SST25WF020 / SST25WF040
Pin Description
EOL Data Sheet
Top View
CE#
SO
WP#
VSS
1 8 VDD
2 7 RST#/HOLD#
3 6 SCK
4 5 SI
1328.25WF 08-soic-P0.0
8-Lead SOIC
CE# 1
SO 2
WP# 3
VSS 4
Top View
8 VDD
7 RST#/HOLD#
6 SCK
5 SI
1328 08-wson P2.0
8-Contact WSON
Figure 2: Pin Assignment for 8-Lead SOIC and 8-Contact WSON
Table 1: Pin Description
Symbol
SCK
SI
SO
CE#
WP#
RST#/
HOLD#
VDD
VSS
Pin Name
Functions
Serial Clock
To provide the timing of the serial interface.
Commands, addresses, or input data are latched on the rising edge of the
clock input, while output data is shifted out on the falling edge of the clock
input.
Serial Data Input To transfer commands, addresses, or data serially into the device.
Inputs are latched on the rising edge of the serial clock.
Serial Data Output To transfer data serially out of the device.
Data is shifted out on the falling edge of the serial clock.
Flash busy status pin in AAI mode if SO is configured as a hardware RY/BY#
pin. See “End-of-Write Detection” on page 16. for more information.
Chip Enable
The device is enabled by a high to low transition on CE#. CE# must remain
low for the duration of any command sequence.
Write Protect
The Write Protect (WP#) pin is used to enable/disable BPL bit in the status
register.
Reset
To reset the operation of the device and the internal logic. The device powers
on with RST# pin functionality as default.
Hold
To temporarily stop serial communication with SPI Flash memory while
device is selected. This is selected by an instruction sequence which is
detailed in “Reset/Hold Mode” on page 6.
Power Supply
To provide power supply voltage: 1.65-1.95V for SST25WF512/010/020/040
Ground
T1.0 20005016
©2014 Silicon Storage Technology, Inc.
4
DS20005016C
11/14

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SST25WF512 전자부품, 판매, 대치품
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit 1.8V SPI Serial Flash
SST25WF512 / SST25WF010 / SST25WF020 / SST25WF040
EOL Data Sheet
Hold
The Hold operation enables the hold pin functionality of the RST#/HOLD# pin. Once set to hold pin
mode, the RST#/HOLD# pin continues functioning as a hold pin until the device is powered off and
then powered on. After a power-off and power-on, the pin functionality returns to a reset pin (RST#)
mode. See “Enable-Hold (EHLD)” on page 22 for detailed timing of the Hold instruction.
In the hold mode, serial sequences underway with the SPI Flash memory are paused without resetting
the clocking sequence. To activate the HOLD# mode, CE# must be in active low state. The HOLD#
mode begins when the SCK active low state coincides with the falling edge of the HOLD# signal. The
Hold mode ends when the rising edge of the HOLD# signal coincides with the SCK active low state. If
the falling edge of the HOLD# signal does not coincide with the SCK active low state, then the device
enters Hold mode when the SCK next reaches the active low state. Similarly, if the rising edge of the
HOLD# signal does not coincide with the SCK active low state, then the device exits Hold mode when
the SCK next reaches the active low state. See Figure 5 for Hold Condition waveform.
Once the device enters Hold mode, SO will be in high-impedance state while SI and SCK can be VIL or VIH.
If CE# is driven active high during a Hold condition, the device returns to standby mode. The device
can then be re-initiated with the command sequences listed in Tables 9 and 10. As long as HOLD# sig-
nal is low, the memory remains in the Hold condition. To resume communication with the device,
HOLD# must be driven active high, and CE# must be driven active low. See Figure 5 for Hold timing.
SCK
HOLD#
Active
Hold
Figure 5: Hold Condition Waveform
Active
Hold
Active
1328 Fx5.0
Write Protection
SST25WF512/010/020/040 provide software Write protection. The Write Protect pin (WP#) enables or
disables the lock-down function of the status register. The Block-Protection bits (BP2, BP1, BP0, and
BPL) in the status register provide Write protection to the memory array and the status register. See
Table 5 for the Block-Protection description.
Write Protect Pin (WP#)
The Write Protect (WP#) pin enables the lock-down function of the BPL bit (bit 7) in the status register.
When WP# is driven low, the execution of the Write-Status-Register (WRSR) instruction is determined by
the value of the BPL bit (see Table 3). When WP# is high, the lock-down function of the BPL bit is disabled.
Table 3: Conditions to execute Write-Status-Register (WRSR) Instruction
WP#
L
L
H
BPL
1
0
X
Execute WRSR Instruction
Not Allowed
Allowed
Allowed
T3.0 20005016
©2014 Silicon Storage Technology, Inc.
7
DS20005016C
11/14

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SST25WF512

1.8V SPI Serial Flash

Microchip
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SST25WF512

1.8V SPI Serial Flash

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