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PDF SST39VF3201C Data sheet ( Hoja de datos )
| Número de pieza | SST39VF3201C | |
| Descripción | 32 Mbit (x16) Multi-Purpose Flash Plus | |
| Fabricantes | Microchip | |
| Logotipo |  |
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32 Mbit (x16) Multi-Purpose Flash Plus
SST39VF3201C / SST39VF3202C
Data Sheet
The SST39VF3201C and SST39VF3202C devices are 2M x16, CMOS Multi-Pur-
pose Flash Plus (MPF+) manufactured with proprietary, high performance CMOS
SuperFlash technology. The split-gate cell design and thick-oxide tunneling injec-
tor attain better reliability and manufacturability compared with alternate
approaches. The SST39VF3201C and SST39VF3202C write (Program or Erase)
with a 2.7-3.6V power supply. This device conforms to JEDEC standard pinouts
for x16 memories.
Features
• Organized as 2M x16
• Single Voltage Read and Write Operations
– 2.7-3.6V
• Superior Reliability
– Endurance: 100,000 Cycles (Typical)
– Greater than 100 years Data Retention
• Low Power Consumption (typical values at 5 MHz)
– Active Current: 6 mA (typical)
– Standby Current: 4 µA (typical)
– Auto Low Power Mode: 4 µA (typical)
• Hardware Block-Protection/WP# Input Pin
– Top Block-Protection (top two 4-KWord blocks)
for SST39VF3202C
– Bottom Block-Protection (bottom two 4-KWord blocks)
for SST39VF3201C
• Sector-Erase Capability
– Uniform 2 KWord sectors
• Block-Erase Capability
– Flexible block architecture
– Eight 4-KWord blocks, 63 32-KWord blocks
• Chip-Erase Capability
• Erase-Suspend/Erase-Resume Capabilities
• Hardware Reset Pin (RST#)
• Security-ID Feature
– Microchip: 128 bits; User: 128 words
• Fast Read Access Time:
– 70 ns
• Latched Address and Data
• Fast Erase and Word-Program:
– Sector-Erase Time: 18 ms (typical)
– Block-Erase Time: 18 ms (typical)
– Chip-Erase Time: 35 ms (typical)
– Word-Program Time: 7 µs (typical)
• Automatic Write Timing
– Internal VPP Generation
• End-of-Write Detection
– Toggle Bits
– Data# Polling
– RY/BY# Pin
• CMOS I/O Compatibility
• JEDEC Standard
– Flash EEPROM Pin Assignments
• Packages Available
– 48-lead TSOP (12mm x 20mm)
– 48-ball TFBGA (6mm x 8mm)
• All devices are RoHS compliant
©2014 Silicon Storage Technology, Inc.
www.microchip.com
DS20005020B
07/14
1 page  
32 Mbit Multi-Purpose Flash Plus
SST39VF3201C / SST39VF3202C
Data Sheet
Table 1: Pin Description
Symbol Pin Name
Functions
AMS1-A0
Address Inputs
To provide memory addresses.
During Sector-Erase AMS-A11 address lines will select the sector.
During Block-Erase AMS-A15 address lines will select the block.
DQ15-DQ0 Data Input/output To output data during Read cycles and receive input data during Write cycles.
Data is internally latched during a Write cycle.
The outputs are in tri-state when OE# or CE# is high.
WP#
Write Protect
To protect the top/bottom boot block from Erase/Program operation when
grounded.
RST#
Reset
To reset and return the device to Read mode.
CE#
Chip Enable
To activate the device when CE# is low.
OE#
Output Enable To gate the data output buffers.
WE#
Write Enable
To control the Write operations.
VDD Power Supply To provide power supply voltage: 2.7-3.6V
VSS Ground
NC No Connection Unconnected pins.
RY/BY#
Ready/Busy#
To output the status of a Program or Erase operation
RY/BY# is a open drain output, so a 10K - 100K pull-up resistor is required
to allow RY/BY# to transition high indicating the device is ready to read.
1. AMS = Most significant address
AMS = A20 for SST39VF3201C/3202C
T1.0 20005020
©2014 Silicon Storage Technology, Inc.
5
DS20005020B
07/14
5 Page 
32 Mbit Multi-Purpose Flash Plus
SST39VF3201C / SST39VF3202C
Ready/Busy# (RY/BY#)
Data Sheet
The devices include a Ready/Busy# (RY/BY#) output signal. RY/BY# is an open drain output pin that
indicates whether an Erase or Program operation is in progress. Since RY/BY# is an open drain out-
put, it allows several devices to be tied in parallel to VDD via an external pull-up resistor. After the rising
edge of the final WE# pulse in the command sequence, the RY/BY# status is valid.
When RY/BY# is actively pulled low, it indicates that an Erase or Program operation is in progress.
When RY/BY# is high (Ready), the devices may be read or left in standby mode.
Data Protection
The SST39VF3201C/3202C provide both hardware and software features to protect nonvolatile data
from inadvertent writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a write cycle.
VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 1.5V.
Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This pre-
vents inadvertent writes during power-up or power-down.
Hardware Block Protection
The SST39VF3202C support top hardware block protection, which protects the top two 4-KWord
blocks of the device. The SST39VF3201C support bottom hardware block protection, which protects
the bottom two 4-KWord blocks of the device. The Boot Block address ranges are described in Table 4.
Program and Erase operations are prevented on the two 4-KWord blocks when WP# is low. If WP# is
left floating, it is internally held high via a pull-up resistor, and the Boot Block is unprotected, enabling
Program and Erase operations on that block.
Table 4: Boot Block Address Ranges
Product
Bottom Boot Block
SST39VF3201C
Top Boot Block
SST39VF3202C
Address Range
000000H-001FFFH
1FE000H-1FFFFFH
T4.0 20005020
Hardware Reset (RST#)
The RST# pin provides a hardware method of resetting the device to read array data. When the RST#
pin is held low for at least TRP, any in-progress operation will terminate and return to Read mode. When
no internal Program/Erase operation is in progress, a minimum period of TRHR is required after RST#
is driven high before a valid Read can take place. See Figure 17.
The Erase or Program operation that has been interrupted needs to be re-initiated after the device
resumes normal operation mode to ensure data integrity.
©2014 Silicon Storage Technology, Inc.
11
DS20005020B
07/14
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SST39VF3201C.PDF ] | |
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