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SST49LF080A 데이터시트 PDF




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부품번호 SST49LF080A 기능
기능 8 Mbit LPC Flash
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SST49LF080A 데이터시트, 핀배열, 회로
8 Mbit LPC Flash
SST49LF080A
Data Sheet
The SST49LF080A flash memory device is designed to interface with the LPC
bus for PC and Internet Appliance application in compliance with Intel Low Pin
Count (LPC) Interface Specification 1.0. Two interface modes are supported: LPC
mode for in-system operations and Parallel Programming (PP) mode to interface
with programming equipment. The SST49LF080A flash memory device is manu-
factured with proprietary, high-performance SuperFlash® Technology. The split-
gate cell design and thick-oxide tunneling injector attain better reliability and man-
ufacturability compared with alternate approaches
Features
• LPC Interface Flash
– SST49LF080A: 1024K x8 (8 Mbit)
• Conforms to Intel LPC Interface Specification 1.0
• Flexible Erase Capability
– Uniform 4 KByte Sectors
– Uniform 64 KByte overlay blocks
– 64 KByte Top Boot Block protection
– Chip-Erase for PP Mode Only
• Single 3.0-3.6V Read and Write Operations
• Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
• Low Power Consumption
– Active Read Current: 6 mA (typical)
– Standby Current: 10 µA (typical)
• Fast Sector-Erase/Byte-Program Operation
– Sector-Erase Time: 18 ms (typical)
– Block-Erase Time: 18 ms (typical)
– Chip-Erase Time: 70 ms (typical)
– Byte-Program Time: 14 µs (typical)
– Chip Rewrite Time: 16 seconds (typical)
– Single-pulse Program or Erase
– Internal timing generation
• Two Operational Modes
– Low Pin Count (LPC) Interface mode for
in-system operation
– Parallel Programming (PP) Mode for fast production pro-
gramming
• LPC Interface Mode
– 5-signal communication interface supporting byte Read
and Write
– 33 MHz clock frequency operation
– WP# and TBL# pins provide hardware write protect for
entire chip and/or top boot block
– Standard SDP Command Set
– Data# Polling and Toggle Bit for End-of-Write detection
– 5 GPI pins for system design flexibility
– 4 ID pins for multi-chip selection
• Parallel Programming (PP) Mode
– 11-pin multiplexed address and 8-pin data
I/O interface
– Supports fast programming In-System on
programmer equipment
• CMOS and PCI I/O Compatibility
• Packages Available
– 32-lead PLCC
– 32-lead TSOP (8mm x 14mm)
• All non-Pb (lead-free) devices are RoHS compliant
©2014 Silicon Storage Technology, Inc.
www.microchip.com
DS20005086B
11/14




SST49LF080A pdf, 반도체, 판매, 대치품
Pin Assignments
8 Mbit LPC Flash
SST49LF080A
Data Sheet
A7(GPI1)
A6 (GPI0)
A5 (WP#)
A4 (TBL#)
A3 (ID3)
A2 (ID2)
A1 (ID1)
A0 (ID0)
DQ0 (LAD0)
4 3 2 1 32 31 30
5 29
6 28
7 27
8 26
32-lead PLCC
9 25
10
Top View
24
11 23
12 22
13 21
14 15 16 17 18 19 20
MODE (MODE)
NC (CE#)
NC
NC
VDD (VDD)
OE# (INIT#)
WE# (LFRAME#)
NC
DQ7 (RES)
( ) Designates LPC Mode
Figure 2: Pin Assignments for 32-lead PLCC
1235 32-plcc P1.0
NC
NC
NC
NC (CE#)
MODE (MODE)
A10 (GPI4)
R/C# (LCLK)
VDD (VDD)
NC
RST# (RST#)
A9 (GPI3)
A8 (GPI2)
A7 (GPI1)
A6 (GPI0)
A5 (WP#)
A4 (TBL#)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
( ) Designates LPC Mode
Standard Pinout
Top View
Die Up
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1235 32-tsop P2.0
OE# (INIT#)
WE# (LFRAME#)
VDD (VDD)
DQ7 (RES)
DQ6 (RES)
DQ5 (RES)
DQ4 (RES)
DQ3 (LAD3)
VSS (VSS)
DQ2 (LAD2)
DQ1 (LAD1)
DQ0 (LAD0)
A0 (ID0)
A1 (ID1)
A2 (ID2)
A3 (ID3)
Figure 3: Pin Assignments for 32-lead TSOP (8mm x 14mm)
©2014 Silicon Storage Technology, Inc.
4
DS20005086B
11/14

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SST49LF080A 전자부품, 판매, 대치품
8 Mbit LPC Flash
SST49LF080A
Design Considerations
Data Sheet
SST recommends a high frequency 0.1 µF ceramic capacitor to be placed as close as possible
between VDD and VSS less than 1 cm away from the VDD pin of the device. Additionally, a low fre-
quency 4.7 µF electrolytic capacitor from VDD to VSS should be placed within 5 cm of the VDD pin. If you
use a socket for programming purposes add an additional 1-10 µF next to each socket.
Product Identification
The Product Identification mode identifies the device as the SST49LF080A and manufacturer as SST.
Table 2: Product Identification
Manufacturer’s ID
Device ID
SST49LF080A
Address
0000H
0001H
Data
BFH
5BH
T2.0 25026
Mode Selection
The SST49LF080A flash memory devices can operate in two distinct interface modes: the LPC mode
and the Parallel Programming (PP) mode. The mode pin is used to set the interface mode selection. If
the mode pin is set to logic High, the device is in PP mode. If the mode pin is set Low, the device is in
the LPC mode. The mode selection pin must be configured prior to device operation. The mode pin is
internally pulled down if the pin is left unconnected. In LPC mode, the device is configured to its host
using standard LPC interface protocol. Communication between Host and the SST49LF080A occurs
via the 4-bit I/O communication signals, LAD [3:0] and LFRAME#. In PP mode, the device is pro-
grammed via an 11-bit address and an 8-bit data I/O parallel signals. The address inputs are multi-
plexed in row and column selected by control signal R/C# pin. The row addresses are mapped to the
lower internal addresses (A10-0), and the column addresses are mapped to the higher internal
addresses (AMS-11). See Figure 4, the Device Memory Map, for address assignments.
©2014 Silicon Storage Technology, Inc.
7
DS20005086B
11/14

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