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PDF SST49LF080A Data sheet ( Hoja de datos )
| Número de pieza | SST49LF080A | |
| Descripción | 8 Mbit LPC Flash | |
| Fabricantes | Silicon Storage Technology | |
| Logotipo |  |
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8 Mbit LPC Flash
SST49LF080A
FEATURES:
SST49LF080A8 Mbit LPC Flash
Data Sheet
• LPC Interface Flash
– SST49LF080A: 1024K x8 (8 Mbit)
• Conforms to Intel LPC Interface Specification 1.0
• Flexible Erase Capability
– Uniform 4 KByte Sectors
– Uniform 64 KByte overlay blocks
– 64 KByte Top Boot Block protection
– Chip-Erase for PP Mode Only
• Single 3.0-3.6V Read and Write Operations
• Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
• Low Power Consumption
– Active Read Current: 6 mA (typical)
– Standby Current: 10 µA (typical)
• Fast Sector-Erase/Byte-Program Operation
– Sector-Erase Time: 18 ms (typical)
– Block-Erase Time: 18 ms (typical)
– Chip-Erase Time: 70 ms (typical)
– Byte-Program Time: 14 µs (typical)
– Chip Rewrite Time: 16 seconds (typical)
– Single-pulse Program or Erase
– Internal timing generation
• Two Operational Modes
– Low Pin Count (LPC) Interface mode for
in-system operation
– Parallel Programming (PP) Mode for fast production
programming
• LPC Interface Mode
– 5-signal communication interface supporting
byte Read and Write
– 33 MHz clock frequency operation
– WP# and TBL# pins provide hardware write protect
for entire chip and/or top boot block
– Standard SDP Command Set
– Data# Polling and Toggle Bit for End-of-Write
detection
– 5 GPI pins for system design flexibility
– 4 ID pins for multi-chip selection
• Parallel Programming (PP) Mode
– 11-pin multiplexed address and 8-pin data
I/O interface
– Supports fast programming In-System on
programmer equipment
• CMOS and PCI I/O Compatibility
• Packages Available
– 32-lead PLCC
– 32-lead TSOP (8mm x 14mm)
• All non-Pb (lead-free) devices are RoHS compliant
PRODUCT DESCRIPTION
The SST49LF080A flash memory device is designed to
interface with the LPC bus for PC and Internet Appliance
application in compliance with Intel Low Pin Count (LPC)
Interface Specification 1.0. Two interface modes are sup-
ported: LPC mode for in-system operations and Parallel
Programming (PP) mode to interface with programming
equipment.
The SST49LF080A flash memory device is manufactured
with SST’s proprietary, high-performance SuperFlash
Technology. The split-gate cell design and thick-oxide tun-
neling injector attain better reliability and manufacturability
compared with alternate approaches. The SST49LF080A
device significantly improves performance and reliability,
while lowering power consumption. The SST49LF080A
device writes (Program or Erase) with a single 3.0-3.6V
power supply. It uses less energy during Erase and Pro-
gram than alternative flash memory technologies. The total
energy consumed is a function of the applied voltage, cur-
rent and time of application. For any give voltage range, the
SuperFlash technology uses less current to program and
has a shorter erase time; the total energy consumed during
any Erase or Program operation is less than alternative
flash memory technologies. The SST49LF080A product
provides a maximum Byte-Program time of 20 µsec. The
entire memory can be erased and programmed byte-by-
byte typically in 16 seconds when using status detection
features such as Toggle Bit or Data# Polling to indicate the
completion of Program operation. The SuperFlash technol-
ogy provides fixed Erase and Program time, independent
of the number of Erase/Program cycles that have per-
formed. Therefore the system software or hardware does
not have to be calibrated or correlated to the cumulative
number of Erase cycles as is necessary with alternative
flash memory technologies, whose Erase and Program
time increase with accumulated Erase/Program cycles.
To meet high density, surface mount requirements, the
SST49LF080A device is offered in 32-lead TSOP and 32-
lead PLCC packages. See Figures 2 and 3 for pin assign-
ments and Table 1 for pin descriptions.
©2006 Silicon Storage Technology, Inc.
S71235-02-000
5/06
1
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
Intel is a registered trademark of Intel Corporation.
These specifications are subject to change without notice.
1 page  
8 Mbit LPC Flash
SST49LF080A
LIST OF TABLES
Data Sheet
TABLE 1: Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
TABLE 2: Product Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
TABLE 3: Address bits definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
TABLE 4: Address Decoding Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
TABLE 5: LPC Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
TABLE 6: LPC Write Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
TABLE 7: Multiple Device Selection Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
TABLE 8: General Purpose Inputs Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
TABLE 9: Memory Map Register Addresses for SST49LF080A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
TABLE 10: Operation Modes Selection (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
TABLE 11: Software Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
TABLE 12: DC Operating Characteristics (All Interfaces) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
TABLE 13: Recommended System Power-up Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
TABLE 14: Pin Capacitance (VDD=3.3V, Ta=25 °C, f=1 Mhz, other pins open) . . . . . . . . . . . . . . . . . . . . 28
TABLE 15: Reliability Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
TABLE 16: Clock Timing Parameters (LPC Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
TABLE 17: Reset Timing Parameters, VDD=3.0-3.6V (LPC Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
TABLE 18: Read/Write Cycle Timing Parameters, VDD=3.0-3.6V (LPC Mode) . . . . . . . . . . . . . . . . . . . . . 31
TABLE 19: AC Input/Output Specifications (LPC Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
TABLE 20: Interface Measurement Condition Parameters (LPC Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . 32
TABLE 21: Read Cycle Timing Parameters, VDD=3.0-3.6V (PP Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . 33
TABLE 22: Program/Erase Cycle Timing Parameters, VDD=3.0-3.6V (PP Mode) . . . . . . . . . . . . . . . . . . . 33
TABLE 23: Reset Timing Parameters, VDD=3.0-3.6V (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
TABLE 24: Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
©2006 Silicon Storage Technology, Inc.
5
S71235-02-000
5/06
5 Page 
8 Mbit LPC Flash
SST49LF080A
CE#
The CE# pin, enables and disables the SST49LF080A,
controlling read and write access of the device. To enable
the SST49LF080A, the CE# pin must be driven low one
clock cycle prior to LFRAME# being driven low. The device
will enter standby mode when internal Write operations are
completed and CE# is high.
LFRAME#
The LFRAME# signifies the start of a (frame) bus cycle or
the termination of an undesired cycle. Asserting LFRAME#
for two or more clock cycle and driving a valid START value
on LAD[3:0] will initiate device operation. The device will
enter standby mode when internal operations are com-
pleted and LFRAME# is high.
TBL#, WP#
The Top Boot Lock (TBL#) and Write Protect (WP#) pins
are provided for hardware write protection of device mem-
ory. The TBL# pin is used to Write-Protect 16 boot sectors
(64 KByte) at the highest memory address range for the
SST49LF080A. The WP# pin write protects the remaining
sectors in the flash memory.
An active low signal at the TBL# pin prevents Program and
Erase operations of the top boot sectors. When TBL# pin is
held high, the write protection of the top boot sectors is dis-
abled. The WP# pin serves the same function for the
remaining sectors of the device memory. The TBL# and
WP# pins write protection functions operate independently
of one another.
Data Sheet
Both TBL# and WP# pins must be set to their required pro-
tection states prior to starting a Program or Erase opera-
tion. A logic level change occurring at the TBL# or WP# pin
during a Program or Erase operation could cause unpre-
dictable results.
INIT#, RST#
A VIL on INIT# or RST# pin initiates a device reset. INIT#
and RST# pins have the same function internally. It is
required to drive INIT# or RST# pins low during a system
reset to ensure proper CPU initialization. During a Read
operation, driving INIT# or RST# pins low deselects the
device and places the output drivers, LAD[3:0], in a high-
impedance state. The reset signal must be held low for a
minimal duration of time TRSTP. A reset latency will occur if
a reset procedure is performed during a Program or Erase
operation. See Table 17, Reset Timing Parameters for
more information. A device reset during an active Program
or Erase will abort the operation and memory contents may
become invalid due to data being altered or corrupted from
an incomplete Erase or Program operation.
System Memory Mapping
The LPC interface protocol has address length of 32-bit or
4 GByte. The SST49LF080A will respond to addresses in
the range as specified in Table 4.
Refer to “Multiple Device Selection” section for more detail
on strapping multiple SST49LF080A devices to increase
memory densities in a system and “Registers” section on
valid register addresses.
TABLE 4: Address Decoding Range
ID Strapping
Device Access
Address Range
Memory Size
Device #0 - 3
Memory Access
FFFF FFFFH : FFC0 0000H
4 MByte
Register Access
FFBF FFFFH : FF80 0000H
4 MByte
Device #4 - 7
Memory Access
FF7F FFFFH : FF40 0000H
4 MByte
Register Access
FF3F FFFFH : FF00 0000H
4 MByte
Device #8 - 11
Memory Access
FEFF FFFFH : FEC0 0000H
4 MByte
Register Access
FEBF FFFFH : FE80 0000H
4 MByte
Device #12 - 15
Memory Access
FE7F FFFFH : FE40 0000H
4 MByte
Register Access
FE3F FFFFH : FE00 0000H
4 MByte
Device #01
Memory Access
000F FFFFH : 000E 0000H
128 KByte
T4.0 1235
1. For device #0 (Boot Device), SST49LF080A decodes the physical addresses of the top 2 blocks (including Boot Block) both at
system memory ranges FFFF FFFFH to FFFE 0000H and 000F FFFFH to 000E 0000H.
©2006 Silicon Storage Technology, Inc.
11
S71235-02-000
5/06
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SST49LF080A.PDF ] | |
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