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기능 1 MEG x 4 DRAM
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MT4C4001J 데이터시트, 핀배열, 회로
DRAM
MT4C4001J
1 MEG x 4 DRAM
Fast Page Mode DRAM
AVAILABLE AS MILITARY
SPECIFICATIONS
• SMD 5962-90847
• MIL-STD-883
FEATURES
• Industry standard x4 pinout, timing, functions, and
packages
• High-performance, CMOS silicon-gate process
• Single +5V±10% power supply
• Low-power, 2.5mW standby; 300mW active, typical
• All inputs, outputs, and clocks are fully TTL and CMOS
compatible
• 1,024-cycle refresh distributed across 16ms
• Refresh modes: RAS\-ONLY, CAS\-BEFORE-RAS\ (CBR),
and HIDDEN
• FAST PAGE MODE access cycle
• CBR with WE\ a HIGH (JEDEC test mode capable via
WCBR)
OPTIONS
• Timing
70ns access
80ns access
MARKING
-7
-8
PIN ASSIGNMENT
(Top View)
20-Pin DIP (C, CN)
DQ1
DQ2
WE\
RAS\
A9
A0
A1
A2
A3
Vcc
1
2
3
4
5
6
7
8
9
10
20 Vss
19 DQ4
18 DQ3
17 CAS\
16 OE\
15 A8
14 A7
13 A6
12 A5
11 A4
20-Pin DIP (CZ)
20-Pin SOJ (ECJ,ECJA),
20-Pin LCC (ECN), &
20-Pin Gull Wing (ECG)
DQ1
DQ2
WE\
RAS\
A9
1
2
3
4
5
A0 9
A1 10
A2 11
A3 12
Vcc 13
26 Vss
25 DQ4
24 DQ3
23 CAS\
22 OE\
18 A8
17 A7
16 A6
15 A5
14 A4
OE\ 1
DQ3 3
Vss 5
DQ2 7
RAS\ 9
A0 11
A2 13
Vcc 15
A5 17
A7 19
2 CAS\
4 DQ4
6 DQ1
8 WE\
10 A9
12 A1
14 A3
16 A4
18 A6
20 A8
100ns access
120ns access
-10
-12
GENERAL DESCRIPTION
The MT4C4001J is a randomly accessed solid-state memory
• Packages
Ceramic DIP (300 mil)
Ceramic DIP (400 mil)
Ceramic LCC*
Ceramic ZIP
Ceramic SOJ
Ceramic SOJ w/ Cu J-lead
Ceramic Gull Wing
CN
C
ECN
CZ
ECJ
ECJA
ECG
No. 103
No. 104
No. 202
No. 400
No. 504
No. 504A
No. 600
containing 4,194,304 bits organized in a x4 conguration. Dur-
ing READ or WRITE cycles each bit is uniquely addressed
through the 20 address bits which are entered 10 bits (A0-
A9) at a time. RAS\ is used to latch the rst 10 bits and CAS\
the later 10 bits. A READ or WRITE cycle is selected with
the WE\ input. A logic HIGH on WE\ dictates READ mode
while a logic LOW on WE\ dictates WRITE mode. During a
WRITE cycle, data-in (D) is latched by the falling edge of WE\
or CAS\, whichever occurs last. If WE\ goes LOW prior to
CAS\ going LOW, the output pin(s) remain open (High-Z) until
*NOTE: If solder-dip and lead-attach is desired on LCC pack- the next CAS\ cycle. If WE\ goes LOW after data reaches the
ages, lead-attach must be done prior to the solder-dip opera- output pin(s), Qs are activated and retain the selected cell data
tion. as long as CAS\ remains low (regardless of WE\ or RAS\).
This LATE WE\ pulse results in a READ-WRITE cycle. The
For more products and information
please visit our web site at
www.micross.com
four data inputs and four data outputs are routed through four
pins using common I/O and pin direction is controlled by WE\
and OE\. FAST-PAGE-MODE operations allow faster data
operations (READ, WRITE, or READ-MODIFY-WRITE)
within a row address (A0-A9) dened page boundary. The
FAST PAGE MODE
(continued)
MT4C4001J
Rev. 2.3 03/10
Micross Components reserves the right to change products or specications without notice.
1




MT4C4001J pdf, 반도체, 판매, 대치품
DRAM
MT4C4001J
ABSOLUTE MAXIMUM RATINGS*
*Stresses greater than those listed under “Absolute Maximum
Voltage on Any Pin Relative to Vss.................-1.0V to +7.0V Ratings” may cause permanent damage to the device. This is a
Storage Temperature.......................................-65oC to +150oC stress rating only and functional operation of the device at these
Power Dissipation.................................................................1W or any other conditions above those indicated in the operation
Short Circuit Output Current...........................................50mA section of this specication is not implied.
Exposure to
Lead Temperature (soldering 5 seconds).....................+270oC absolute maximum rating conditions for extended periods may
affect reliability.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(NOTES: 1, 3, 4, 6, 7) (-55°C < TA < 125°C; VCC = 5V ±10%)
PARAMETER/CONDITION
Supply Voltage
Input High (Logic 1) Voltage, All Inputs
Input Low (Logic 0) Voltage, All Inputs
INPUT LEAKAGE CURRENT
Any Input 0V < VIN < 5.5V Vcc = 5.5V
(All other pints not under test = 0V)
OUTPUT LEAKAGE CURRENT
(Q is Disabled, 0V < VOUT < 5.5V) Vcc = 5.5V
SYM
VCC
VIH
VIL
II
IOZ
MIN
MAX
UNITS NOTES
4.5 5.5
V
2.4 VCC+0.5
-0.5 0.8
V
V
-5 5 μA
-5 5 μA
OUTPUT LEVELS
Output High Voltage (IOUT = -5mA)
Output Low Voltage (IOUT = 4.2mA)
VOH
VOL
2.4
0.4
V
V
PARAMETER/CONDITION
STANDBY CURRENT (TTL)
(RAS\ = CAS\ = VIH)
STANDBY CURRENT (CMOS)
(RAS\ = CAS\ = VCC -0.2V; all other inputs = VCC -0.2V)
OPERATING CURRENT: Random READ/WRITE
Average Power-Supply Current
(RAS\, CAS\, Address Cycling: tRC = tRC(MIN))
OPERATING CURRENT: FAST PAGE MODE
Average Power-Supply Current
(RAS\ = VIL, CAS\, Address Cycling: tPC = tPC (MIN))
REFRESH CURRENT: RAS\-ONLY
Average Power-Supply Current
(RAS\ Cycling, CAS\ = VIH: tRC = tRC (MIN))
REFRESH CURRENT: CAS\-BEFORE-RAS\
Average Power-Supply Current
(RAS\, CAS\, Address Cycling: tRC = tRC (MIN))
SYM
ICC1
ICC2
-7
4
2
MAX
-8 -10
44
-12 UNITS NOTES
4 mA
2 2 2 mA
ICC3 85 75 65 70 mA 3, 4
ICC4 60 50 45 40 mA 3, 4
ICC5
85 75 65 70
mA
3
ICC6 85 75 65 70 mA 3, 5
MT4C4001J
Rev. 2.3 03/10
Micross Components reserves the right to change products or specications without notice.
4

4페이지










MT4C4001J 전자부품, 판매, 대치품
DRAM
MT4C4001J
NOTES:
1. All voltages referenced to Vss.
2. This parameter is sampled, not 100% tested. Capacitance is
measured with Vcc=5V, f=1 MHz
25°C ±3°C, Vbias = 2.4V applied
atot leeascshthiannpu5t0amnVdrmso, uTtpAu=t
individually with remaining inputs and outputs open.
3. Icc is dependent on cycle rates.
4. Icc is dependent on output loading and cycle rates. Speci-
ed values are obtained with minimum cycle time and the
output open.
5. Enables on-chip refresh and address counters.
6. The minimum specications are used only to indicate cycle
time at which proper operation over the full temperature range
(7-.5A5°nCin<itTiaAl
< 125°C) is assured.
pause of 100μs is required
after
power-up
fol-
lowed by eight RAS\ refresh cycles (RAS\-ONLY or CBR with
WE\ HIGH) before proper device operation is assured. The
eight RAS\ cycle wake-up should be repeated any time the
16ms refresh requirement is exceeded.
8. AC characteristics assume tT = 5ns.
s9u. VrinIHg(tMimINin)gaonfdiVnpILu(tMsiAgnXa)lsa.reTrreafnerseitniocenlteivmeelss
for
are
mea-
mea-
sured
10. In
between
addition
VtoIHmaenedtiVngILt(hoer
tbreatnwsieteionnVraILteanspdeVciIHc).ation,
all
input signals must transit between VIH and VIL (or between VIL
and VIH) in a monotonic manner.
11. If CAS\ = VIH, data outputs (DQs) are High-Z.
12.
the
lIafsCt AvaSli\d=RVEIAL,Ddactyacoleu.tputs
(DQs)
may
contain
data
from
13. Measured with a load equivalent to two TTL gates and
100pF.
14. Assumes that tRCD < tRCD (MAX). If tRCD is greater than the
maximum recommended value shown in this table, tRAC will
increase by the amount that tRCD exceeds the value shown.
15.
16.
AIfsCsuAmSe\sisthLaOt tWRCDat>thtReCfDal(lMingAeXd)ge
of
RAS\,
DQs
will
be
maintained from the previous cycle. To initiate a new cycle
and clear the data out buffer, CAS\ must be pulsed HIGH for
tCPN.
17. Operation within the tRCD (MAX) limit ensures that tRAC
(MAX) can be met. tRCD (MAX) is specied as a reference
point only; if tRCD is greater than the specied tRCD (MAX) limit,
then access time is controlled exclusively by tCAC.
18. Operation within the tRAD (MAX) limit ensures that tRCD
(MAX) can be met. tRAD (MAX) is specied as a reference
point only; if tRAD is greater than the specied tRAD (MAX)
limit, then access time is controlled exclusively by tAA.
19. Either tRCH or tRRH must be satised for a READ cycle.
20. tOFF (MAX) denes the time at which the output achieves the
open circuit conditions and is not referenced to VOH or VOL.
21. tWCS, tRWD, tAWD, and tCWD are not restrictive operating pa-
rameters. tWCS applies to EARLY-WRITE cycles. tRWD, tAWD,
and tCWD apply to READ-MODIFY-WRITE cycles. If tWCS
d>attWa CoSu(tpMuItNw)i,ltlhreemcyacinleains
an EARLY-WRITE cycles and the
open circuit throughout the entire
cycle. If tRWD > tRWD (MIN), tAWD > tAWD (MIN) and tCWD >
tdCaWtaD
(MIN), the
output will
cycle is
contain
a READ-MODIFY-WRITE
data read from the selected
and
cell.
the
If
neither of the above conditions is met, the state of the data out
is indeterminate. OE\ held HIGH and WE\ taken LOW after
CAS\ goes LOW results in a LATE-WRITE (OE\ controlled)
cLyAcTleE.-WtWRCSI,TtERWcDy,ctlCeW. D, and tAWD are not
applicable in a
22. These parameters are referenced to CAS\ leading edge
in EARLY-WRITE cycle and WE\ leading edge in LATE-
WRITE cycles and WE\ leading edge in LATE-WRITE or
READ-MODIFY-WRITE cycle.
23. If OE\ is tied permanently LOW, LATE-WRITE or
READ-MODIFY-WRITE operations are not possible.
24. A HIDDEN REFRESH may also be performed after a
WRITE cycle. In this case, WE\=LOW and OE\=HIGH.
25.
pin
tbWeTinSganhedltdWLTOH WaretoseetnuapbalnedthheoJlEdDspEeCcitecsat tmioondsef(owr tihtheCWBER\
timing constraints). These two parameters are the inverts
o2f6.tWLRAPTaEn-dWtWRRITH Einatnhde
CBR REFRESH cycle.
READ-MODIFY-WRITE
cycles
must
ihnavoerdbeorthtotOeDnsaunrde
ttOhEaHt
met (OE\ HIGH during WRITE
the output buffers will be open
cycle)
during
the WRITE cycle. The DQs will provide the previously read
data if CAS\ remains LOW and OE\ is taken back LOW after
ttOheEHDisQms ewt.illIfreCmAaSin\ goopeesnH. IGH prior to OE\ going back LOW,
27. The
cur. If
CDAQSs\ogpoeensdHurIiGnHg RErsAt,DOcEy\clbeescoonmceestOaD“odrotnOFtFcaroec.”-
If OE\ goes HIGH and CAS\ stays LOW, OE\ is not a “don’t
care;” and the DQs will provide the previously read data if OE\
is taken back LOW (while CAS\ remains LOW).
28. JEDEC test mode only.
MT4C4001J
Rev. 2.3 03/10
Micross Components reserves the right to change products or specications without notice.
7

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MT4C4001J

1 MEG x 4 DRAM

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