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PDF MC10210 Data sheet ( Hoja de datos )
| Número de pieza | MC10210 | |
| Descripción | Dual 3-Input / 3-Output OR Fate | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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MC10210
Dual 3-Input/3-Output OR
Gate
The MC10210 is designed to drive up to six transmission lines
simul– taneously. The multiple outputs of this device also allow the
wire “OR”–ing of several levels of gating for minimization of gate and
package count.
The ability to control three parallel lines with minimum propagation
delay from a single point makes the MC10210 particularly useful in
clock distribution applications where minimum clock skew is desired.
• PD = 160 mW typ/pkg (No Loads)
• tpd = 1.5 ns typ (All Output Loaded)
• tr, tf = 1.5 ns typ (20%–80%)
LOGIC DIAGRAM
5
62
73
4
9
10 12
11 13
14
VCC1 = PIN 1, 15
VCC2 = PIN 16
VEE = PIN 8
DIP
PIN ASSIGNMENT
VCC1
AOUT
AOUT
AOUT
AIN
AIN
AIN
VEE
1
2
3
4
5
6
7
8
16 VCC2
15 VCC1
14 BOUT
13 BOUT
12 BOUT
11 BIN
10 BIN
9 BIN
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion Tables on page 18.
http://onsemi.com
CDIP–16
L SUFFIX
CASE 620
PDIP–16
P SUFFIX
CASE 648
PLCC–20
FN SUFFIX
CASE 775
MARKING
DIAGRAMS
16
MC10210L
AWLYYWW
1
16
MC10210P
AWLYYWW
1
1
10210
AWLYYWW
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
ORDERING INFORMATION
Device
Package
Shipping
MC10210L
CDIP–16
25 Units / Rail
MC10210P
PDIP–16
25 Units / Rail
MC10210FN
PLCC–20
46 Units / Rail
© Semiconductor Components Industries, LLC, 2000
March, 2000 – Rev. 6
420
Publication Order Number:
MC10210/D
1 page | ||
| Páginas | Total 3 Páginas | |
| PDF Descargar | [ Datasheet MC10210.PDF ] | |
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