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PDF FDMS86200DC Data sheet ( Hoja de datos )

Número de pieza FDMS86200DC
Descripción MOSFET ( Transistor )
Fabricantes Fairchild Semiconductor　
Logotipo Fairchild Semiconductor Logotipo



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No Preview Available ! FDMS86200DC Hoja de datos, Descripción, Manual

July 2015
FDMS86200DC
N-Channel Dual CoolTM 56 Shielded Gate PowerTrench® MOSFET
150 V, 40 A, 17 mΩ
Features
General Description
„ Shielded Gate MOSFET Technology
„ Dual CoolTM Top Side Cooling PQFN package
„ Max rDS(on) = 17 mΩ at VGS = 10 V, ID = 9.3 A
„ Max rDS(on) = 25 mΩ at VGS = 6 V, ID = 7.8 A
„ High performance technology for extremely low rDS(on)
„ 100% UIL tested
„ RoHS Compliant
This N-Channel MOSFET is produced using Fairchild
Semiconductor’s advanced PowerTrench® process that
incorporates Shielded Gate technology. Advancements in both
silicon and Dual CoolTM package technologies have been
combined to offer the lowest rDS(on) while maintaining excellent
switching performance by extremely low Junction-to-Ambient
thermal resistance.
Applications
„ Primary MOSFET in DC - DC converters
„ Secondary Synchronous rectifier
„ Load switch
Pin 1
D
D
D
D
S
S
D
D
G
S
S
S
Pin 1
Top
Dual CoolTM 56
Bottom
MOSFET Maximum Ratings TA = 25 °C unless otherwise noted
Symbol
VDS
VGS
ID
EAS
PD
TJ, TSTG
Parameter
Drain to Source Voltage
Gate to Source Voltage
Drain Current
-Continuous
-Continuous
-Pulsed
TC = 25 °C
TA = 25 °C
Single Pulse Avalanche Energy
Power Dissipation
TC = 25 °C
Power Dissipation
TA = 25 °C
Operating and Storage Junction Temperature Range
Thermal Characteristics
S
G
(Note 1a)
(Note 4)
(Note 3)
(Note 1a)
D
D
Ratings
150
±20
40
9.3
100
294
125
3.2
-55 to +150
Units
V
V
A
mJ
W
°C
RθJC
RθJC
RθJA
RθJA
RθJA
RθJA
RθJA
Thermal Resistance, Junction to Case
Thermal Resistance, Junction to Case
Thermal Resistance, Junction to Ambient
Thermal Resistance, Junction to Ambient
Thermal Resistance, Junction to Ambient
Thermal Resistance, Junction to Ambient
Thermal Resistance, Junction to Ambient
Package Marking and Ordering Information
(Top Source)
(Bottom Drain)
(Note 1a)
(Note 1b)
(Note 1i)
(Note 1j)
(Note 1k)
2.5
1.0
38
81
16
23
11
°C/W
Device Marking
86200
Device
FDMS86200DC
Package
Dual CoolTM 56
Reel Size
13’’
Tape Width
12 mm
Quantity
3000 units
©2012 Fairchild Semiconductor Corporation
FDMS86200DC Rev. 1.4
1
www.fairchildsemi.com

1 page




FDMS86200DC pdf
Typical Characteristics TJ = 25 °C unless otherwise noted
10
ID = 9.3 A
8
6
4
VDD = 50 V
VDD = 75 V
VDD = 100 V
10000
1000
100
Ciss
Coss
2
0
0 7 14 21 28 35
Qg, GATE CHARGE (nC)
10
f = 1 MHz
VGS = 0 V
1
0.1
1
10
VDS, DRAIN TO SOURCE VOLTAGE (V)
Crss
100
Figure 7. Gate Charge Characteristics
Figure8. CapacitancevsDrain
to Source Voltage
50 60
TJ = 25 oC
10
TJ = 100 oC
TJ = 125 oC
1
0.001
0.1 1
10
tAV, TIME IN AVALANCHE (ms)
Figure9. Unclamped Inductive
Switching Capability
200
100
100
10
1
THIS AREA IS
0.1 LIMITED BY rDS(on)
1 ms
10 ms
100 ms
SINGLE PULSE
1s
0.01
TJ = MAX RATED
RθJA = 81 oC/W
CURVE BENT TO
10 s
DC
TA = 25 oC
0.001
0.01 0.1
MEASURED DATA
1 10 100
800
VDS, DRAIN to SOURCE VOLTAGE (V)
Figure 11. Forward Bias Safe
Operating Area
45
30
Limited by Package
15
VGS = 10 V
VGS = 6 V
RθJC = 1.0 oC/W
0
25 50 75 100 125
TC, CASE TEMPERATURE (oC)
Figure 10. Maximum Continuous Drain
Current vs Case Temperature
150
1000
100
SINGLE PULSE
RθJA = 81 oC/W
TA = 25 oC
10
1
10-3
10-2
10-1
100
101
100 1000
t, PULSE WIDTH (sec)
Figure 12. Single Pulse Maximum
Power Dissipation
©2012 Fairchild Semiconductor Corporation
FDMS86200DC Rev. 1.4
5
www.fairchildsemi.com

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