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FDME910PZT 데이터시트 PDF




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부품번호 FDME910PZT 기능
기능 MOSFET ( Transistor )
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FDME910PZT 데이터시트, 핀배열, 회로
FDME910PZT
P-Channel PowerTrench® MOSFET
-20 V, -8 A, 24 mΩ
Features
„ Max rDS(on) = 24 mΩ at VGS = -4.5 V, ID = -8 A
„ Max rDS(on) = 31 mΩ at VGS = -2.5 V, ID = -7 A
„ Max rDS(on) = 45 mΩ at VGS = -1.8 V, ID = -6 A
„ Low profile: 0.55 mm maximum in the new package MicroFET
1.6x1.6 Thin
„ HBM ESD protection level > 2 kV typical (Note 3)
„ Free from halogenated compounds and antimony oxides
„ RoHS Compliant
February 2015
General Description
This device is designed specifically for battery charging or load
switching in cellular handset and other ultraportable applications.
It features a MOSFET with low on-state resistance and zener
diode protection against ESD. The MicroFET 1.6x1.6 Thin
package offers exceptional thermal performance for its physical
size and is well suited to switching and linear mode applications.
G
D
D
Pin 1
S
S
D
D
Bottom Drain Contact
D1
6D
D2
5D
G3
4S
BOTTOM
TOP
MicroFET 1.6x1.6 Thin
MOSFET Maximum Ratings TA = 25 °C unless otherwise noted
Symbol
VDS
VGS
ID
PD
TJ, TSTG
Parameter
Drain to Source Voltage
Gate to Source Voltage
-Continuous
-Pulsed
TA = 25°C
Power Dissipation
TA = 25°C
Power Dissipation
TA = 25°C
Operating and Storage Junction Temperature Range
Thermal Characteristics
(Note 1a)
(Note 1a)
(Note 1b)
Ratings
-20
±8
-8
-32
2.1
0.7
-55 to +150
Units
V
V
A
W
°C
RθJA
RθJA
Thermal Resistance, Junction to Ambient
Thermal Resistance, Junction to Ambient
Package Marking and Ordering Information
(Note 1a)
(Note 1a)
60
175
°C/W
Device Marking
E91
Device
FDME910PZT
Package
MicroFET 1.6x1.6 Thin
Reel Size
7 ’’
Tape Width
8 mm
Quantity
5000 units
©2012 Fairchild Semiconductor Corporation
FDME910PZT Rev.C3
1
www.fairchildsemi.com




FDME910PZT pdf, 반도체, 판매, 대치품
Typical Characteristics TJ = 25 °C unless otherwise noted
4.5
ID = -8 A
3.0
1.5
VDD = -8 V
VDD = -10 V
VDD = -12 V
0.0
0
4 8 12
Qg, GATE CHARGE (nC)
16
Figure 7. Gate Charge Characteristics
3000
Ciss
1000
Coss
Crss
f = 1 MHz
VGS = 0 V
100
0.1 1 10
-VDS, DRAIN TO SOURCE VOLTAGE (V)
20
Figure8. CapacitancevsDrain
to Source Voltage
10-1
10-2 VDS = 0 V
10-3
10-4
10-5
10-6
10-7
10-8
10-9
10-10
0
3
TJ = 125 oC
TJ = 25 oC
69
12
-VGS, GATE TO SOURCE VOLTAGE (V)
Figure9. GateLeakageCurrent
vs Gate to Source Voltage
100
15
10
50
10
1
0.1
0.01
0.01
1 ms
THIS AREA IS
LIMITED BY rDS(on)
SINGLE PULSE
TJ = MAX RATED
RθJA = 175 oC/W
TA = 25 oC
10 ms
100 ms
1s
10 s
DC
0.1 1 10
-VDS, DRAIN to SOURCE VOLTAGE (V)
100
Figure 10. Forward Bias Safe
Operating Area
SINGLE PULSE
RθJA = 175 oC/W
TA = 25 oC
1
0.1
10-3
10-2
10-1
100
101
t, PULSE WIDTH (sec)
Figure 11. Single Pulse Maximum Power Dissipation
100
1000
©2012 Fairchild Semiconductor Corporation
FDME910PZT Rev.C3
4
www.fairchildsemi.com

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FDME910PZT 전자부품, 판매, 대치품
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FDME910PZT

MOSFET ( Transistor )

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