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PDF FDN86501LZ Data sheet ( Hoja de datos )

Número de pieza FDN86501LZ
Descripción MOSFET ( Transistor )
Fabricantes Fairchild Semiconductor 
Logotipo Fairchild Semiconductor Logotipo



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No Preview Available ! FDN86501LZ Hoja de datos, Descripción, Manual

October 2015
FDN86501LZ
N-Channel Shielded Gate PowerTrench® MOSFET
60 V, 2.6 A, 116 mΩ
Features
General Description
„ Shielded Gate MOSFET Technology
„ Max rDS(on) = 116 mΩ at VGS = 10 V, ID = 2.6 A
„ Max rDS(on) = 173 mΩ at VGS = 4.5 V, ID = 2.1 A
„ High performance trench technology for extremely low rDS(on)
„ High power and current handling capability in a widely used
surface mount package
„ Fast switching speed
„ 100% UIL tested
This N-Channel MOSFET is produced using Fairchild
Semiconductor’s advanced PowerTrench® process that
incorporates Shielded Gate technology. This process has been
optimized for rDS(on), switching performance and ruggedness.
Applications
„ Primary DC-DC Switch
„ Load Switch
„ RoHS Compliant
MOSFET Maximum Ratings TA = 25 °C unless otherwise noted.
Symbol
VDS
VGS
ID
EAS
PD
TJ, TSTG
Parameter
Drain to Source Voltage
Gate to Source Voltage
-Continuous
-Pulsed
Single Pulse Avalanche Energy
Power Dissipation
Power Dissipation
Operating and Storage Junction Temperature Range
Thermal Characteristics
(Note 1a)
(Note 4)
(Note 3)
(Note 1a)
(Note 1b)
Ratings
60
±20
2.6
24
6
1.5
0.6
-55 to +150
Units
V
V
A
mJ
W
°C
RθJC
RθJA
Thermal Resistance, Junction-to-Case
Thermal Resistance, Junction-to-Ambient
Package Marking and Ordering Information
(Note 1)
(Note 1a)
75
80
°C/W
Device Marking
8650
Device
FDN86501LZ
Package
SSOT-3
Reel Size
7 ’’
Tape Width
8 mm
Quantity
3000 units
©2015 Fairchild Semiconductor Corporation
FDN86501LZ Rev.1.1
1
www.fairchildsemi.com

1 page




FDN86501LZ pdf
Typical Characteristics TJ = 25 °C unless otherwise noted.
2
1 DUTY CYCLE-DESCENDING ORDER
0.1
0.01
D = 0.5
0.2
0.1
0.05
0.02
0.01
0.001
SINGLE PULSE
0.0001
10-5
10-4
10-3
10-2
10-1
1
t, RECTANGULAR PULSE DURATION (sec)
PDM
t1
t2
NOTES:
ZθJA(t)
RθJA =
=18r0(t)oCx /RWθJA
Peak TJ = PDM x ZθJA(t) + TA
Duty Cycle, D = t1 / t2
10 100
Figure 13. Junction-to-Ambient Transient Thermal Response Curve
1000
©2015 Fairchild Semiconductor Corporation
FDN86501LZ Rev.1.1
5
www.fairchildsemi.com

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