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PDF FDMS3615S Data sheet ( Hoja de datos )
| Número de pieza | FDMS3615S | |
| Descripción | MOSFET ( Transistor ) | |
| Fabricantes | Fairchild Semiconductor | |
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FDMS3615S
PowerTrench® Power Stage
25V Asymmetric Dual N-Channel MOSFET
August 2011
Features
General Description
Q1: N-Channel
Max rDS(on) = 5.8 mΩ at VGS = 10 V, ID = 16 A
Max rDS(on) = 8.3 mΩ at VGS = 4.5 V, ID = 13 A
Q2: N-Channel
Max rDS(on) = 3.4 mΩ at VGS = 10 V, ID = 18 A
Max rDS(on) = 4.6 mΩ at VGS = 4.5 V, ID = 15 A
Low inductance packaging shortens rise/fall times, resulting in
lower switching losses
MOSFET integration enables optimum layout for lower circuit
inductance and reduced switch node ringing
RoHS Compliant
Pin 1
This device includes two specialized N-Channel MOSFETs in a
dual PQFN package. The switch node has been internally
connected to enable easy placement and routing of synchronous
buck converters. The control MOSFET (Q1) and synchronous
SyncFET (Q2) have been designed to provide optimal power
efficiency.
Applications
Computing
Communications
General Purpose Point of Load
Notebook VCORE
Server
G1 D1 D1 D1
D1
S2 5
Q2
4 D1
PHASE
(S1/D2)
G2S2
S2 S2
Top
Power 56
Bottom
MOSFET Maximum Ratings TA = 25°C unless otherwise noted
S2 6
S2 7
G2 8
PHASE
3 D1
2 D1
Q1 1 G1
Symbol
VDS
VGS
ID
EAS
PD
TJ, TSTG
Parameter
Drain to Source Voltage
Gate to Source Voltage
Drain Current -Continuous (Package limited)
-Continuous (Silicon limited)
-Continuous
-Pulsed
Single Pulse Avalanche Energy
Power Dissipation for Single Operation
Power Dissipation for Single Operation
Operating and Storage Junction Temperature Range
Thermal Characteristics
(Note 3)
TC = 25 °C
TC = 25 °C
TA = 25 °C
TA = 25°C
TA = 25°C
Q1 Q2
25 25
±20 ±20
23 18
89
161a
88
181b
45
384
2.31a
1.01c
36
985
2.31b
1.01d
-55 to +150
Units
V
V
A
mJ
W
°C
RθJA
RθJA
Thermal Resistance, Junction to Ambient
Thermal Resistance, Junction to Ambient
Package Marking and Ordering Information
551a
1251c
551b
1251d
°C/W
Device Marking
Y8OA
K10OC
Device
FDMS3615S
Package
Power 56
Reel Size
13 ”
Tape Width
12 mm
Quantity
3000 units
©2011 Fairchild Semiconductor Corporation
FDMS3615S Rev.C6
1
www.fairchildsemi.com
1 page  
Typical Characteristics (Q1 N-Channel) TJ = 25°C unless otherwise noted
10
ID = 16 A
8
6
4
2
VDD = 10 V
VDD = 13 V
VDD = 16 V
0
0 5 10 15 20
Qg, GATE CHARGE (nC)
Figure 7. Gate Charge Characteristics
3000
1000
Ciss
Coss
100 f = 1 MHz
Crss
VGS = 0 V
50
0.1
1
10
VDS, DRAIN TO SOURCE VOLTAGE (V)
25
Figure8. CapacitancevsDrain
to Source Voltage
20
10 TJ = 25 oC
TJ = 100 oC
TJ = 125 oC
20
15
10
Limited by Package
5
RθJA = 55 oC/W
VGS = 10 V
VGS = 4.5 V
1
0.001
0.01 0.1
1
10
tAV, TIME IN AVALANCHE (ms)
Figure9. UnclampedInductive
Switching Capability
100
100
100 μs
10
1 ms
1 THIS AREA IS
LIMITED BY rDS(on)
10 ms
100 ms
SINGLE PULSE
0.1 TJ = MAX RATED
RθJA = 125 oC/W
TA = 25 oC
0.01
0.01
0.1
1
1s
10s
DC
10 100200
VDS, DRAIN to SOURCE VOLTAGE (V)
Figure 11. Forward Bias Safe
Operating Area
0
25 50 75 100 125 150
TA, AMBIENT TEMPERATURE (oC)
Figure 10. Maximum Continuous Drain
Current vs Ambient Temperature
1000
100
SINGLE PULSE
RθJA = 125 oC/W
10
1
0.5
10-4 10-3 10-2 10-1
1
10
t, PULSE WIDTH (sec)
100 1000
Figure 12. Single Pulse Maximum
Power Dissipation
©2011 Fairchild Semiconductor Corporation
FDMS3615S Rev.C6
5
www.fairchildsemi.com
5 Page 
Application Information
1. Switch Node Ringing Suppression
Fairchild’s Power Stage products incorporate a proprietary design* that minimizes the peak overshoot, ringing voltage on the switch
node (PHASE) without the need of any external snubbing components in a buck converter. As shown in the figure 29, the Power Stage
solution rings significantly less than competitor solutions under the same set of test conditions.
Power Stage Device
Competitors solution
Figure 29. Power Stage phase node rising edge, High Side Turn on
*Patent Pending
©2011 Fairchild Semiconductor Corporation
FDMS3615S Rev.C6
11
www.fairchildsemi.com
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet FDMS3615S.PDF ] | |
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