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부품번호 TOP222YN 기능
기능 Three-Terminal Off-Line PWM Switch
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TOP222YN 데이터시트, 핀배열, 회로
This product is not recommended for new designs.
TOP221-227
TOPSwitch-II Family
Three-Terminal Off-Line PWM Switch
Product Highlights
• Lowest cost, lowest component count switcher solution
• Cost competitive with linears above 5 W
• Very low AC/DC losses – up to 90% efficiency
• Built-in Auto-restart and Current limiting
• Latching Thermal shutdown for system level protection
• Implements Flyback, Forward, Boost or Buck topology
• Works with primary or opto feedback
• Stable in discontinuous or continuous conduction mode
• Source connected tab for low EMI
• Circuit simplicity and Design Tools reduce time to market
Description
The second generation TOPSwitch-II family is more cost
effective and provides several enhancements over the first
generation TOPSwitch family. The TOPSwitch-II family
extends the power range from 100W to 150W for 100/115/
230 VAC input and from 50W to 90W for 85-265 VAC univer-
sal input. This brings TOPSwitch technology advantages
to many new applications, i.e. TV, Monitor, Audio amplifiers,
etc. Many significant circuit enhancements that reduce the
sensitivity to board layout and line transients now make the
design even easier. The standard 8L PDIP package option
AC
IN
D
TOPSwitch
CONTROL C
S
Figure 1. Typical Flyback Application.
PI-1951-091996
reduces cost in lower power, high efficiency applications.
The internal lead frame of this package uses six of its pins to
transfer heat from the chip directly to the board, eliminating
the cost of a heat sink. TOPSwitch incorporates all functions
necessary for a switched mode control system into a three
terminal monolithic IC: power MOSFET, PWM controller, high
voltage start up circuit, loop compensation and fault protec-
tion circuitry.
Output Power Table
TO-220 (Y) Package1
PART
ORDER
NUMBER
Single Voltage Input 3
100/115/230 VAC ±15%
P 4,6
MAX
Wide Range Input
85 to 265 VAC
P 4,6
MAX
TOP221YN
12 W
7W
TOP222YN
25 W
15 W
8L PDIP (P) or 8L SMD (G) Package2
PART
ORDER
NUMBER
Single Voltage Input3
100/115/230 VAC ±15%
P 5,6
MAX
Wide Range Input
85 to 265 VAC
P 5,6
MAX
TOP221 PN or TOP221GN
9W
6W
TOP222 PN or TOP222GN
15 W
10 W
TOP223YN
50 W
30 W
TOP223 PN or TOP223GN
25 W
15 W
TOP224YN
75 W
45 W
TOP224 PN or TOP224GN
30 W
20 W
TOP225YN
100 W
60 W
TOP226YN
125 W
75 W
TOP227YN
150 W
90 W
Notes: 1. Package outline: TO-220/3 2. Package Outline: DIP-8 or SMD-8 3. 100/115 VAC with doubler input 4. Assumes appro-
priate heat sinking to keep the maximum TOPSwitch junction temperature below 100 °C. 5. Soldered to 1 sq. in. (6.45 cm2), 2 oz.
cpoopwpeer rccalpaadb(i6lit1y0ingma /gmiv2)en6a. pPpMAliXciastitohne
maximum practical continuous power output level for conditions
depends on thermal environment, transformer design, efficiency
shown. The continuous
required, minimum spec-
ified input voltage, input storage capacitance, etc. 7. Refer to key application considerations section when using TOPSwitch-II in
an existing TOPSwitch design.
www.power.com
This Product is Covered by Patents and/or Pending Patent Applications.
August 2016




TOP222YN pdf, 반도체, 판매, 대치품
TOP221-227
TOPSwitch-II Family Functional Description (cont.)
Control Voltage Supply
CcoOnNtrToRlleOr LanpdindvroivlteargceirVcCuiitsryt.heAnsuepxptelyrnoarl
bias voltage for the
bypass capacitor
closely connected between the CONTROL and SOURCE
pins is required to supply the gate drive current. The total
amount of capacitance connected to this pin
the auto-restart timing as well as control loop
(cCoTm) palesnossaetitosn.
eVtCicisreregguulalatitoendisinuesiethderfoorfintwitoialmsotadret-supofaonpderoavteiornlo.adHyospteerr-a-
tion. Shunt regulation is used to separate the duty cycle
error signal from the control circuit supply current. During
start-up, CONTROL pin current is supplied from a high-volt-
age switched current source connected internally between
the DRAIN and CONTROL pins. The current source pro-
vides sufficient current to supply the control circuitry as well
as charge the total external capacitance (CT).
vTohletafgirestctuimrreenVtCsroeuarccheeiss
the upper
turned off
threshold, the
and the PWM
high-
modulator
and output transistor are activated, as shown in Figure 5(a).
During normal operation (when the output voltage is regulat-
TCehdOe)NfseTheRudOnbtLarcepkginuclfoaenteotdrrobklaecceukprrsceunVrtCresauntpttyeppxliciecesaeltlhdyein5Vg.7CthVseubpryepqslyhuucirnuetrdirneDgnCt.
supply current through the PWM error signal sense resistor
RgaE.inTohfethloewerdryonr aammipcliifmiepr ewdhaenncuesoefdthinisappinri(mZaC)rysefetsedthbeack
configuration. The dynamic impedance of the CONTROL
pin together with the external resistance and capacitance
determines the control loop compensation of the power
system.
If the CONTROL
discharge to the
ploiwn etor ttahlreesxhteorlnda,lthceapoauctpitaunt cMeO(SCFT)EsThiosuld
turned off and the control circuit is placed in a low-current
standby mode. The high-voltage current source turns on
and charges the external capacitance again. Charging
current is shown with a negative polarity and discharging
current is shown with a positive polarity in Figure 6. The
hysteretic auto-restart comparator
of typically 4.7 to 5.7 V by turning
tkheeehpigs hV-Cvowltitahgine
a window
current
source on and off as shown in Figure 5(b). The auto-restart
circuit has a divide-by-8 counter which prevents the output
MOSFET from turning on again until eight discharge-charge
cycles have elapsed. The counter effectively limits
TOPSwitch power dissipation by reducing the auto-restart
duty cycle to typically 5%. Auto-restart continues to cycle
until output voltage regulation is again achieved.
Bandgap Reference
All critical TOPSwitch internal voltages are derived from a
temperature-compensated bandgap reference. This refer-
ence is also used to generate a temperature-compensated
current source which is trimmed to accurately set the oscilla-
tor frequency and MOSFET gate drive current.
Oscillator
The internal oscillator linearly charges and discharges the
internal capacitance between two voltage levels to create a
sawtooth waveform for the pulse width modulator. The oscil-
lator sets the pulse width modulator/current limit latch at the
beginning of each cycle. The nominal frequency of 100 kHz
was chosen to minimize EMI and maximize efficiency in
power supply applications. Trimming of the current reference
improves the frequency accuracy.
Pulse Width Modulator
The pulse width modulator implements a voltage-mode
control loop by driving the output MOSFET with a duty cycle
inversely proportional to the current into the CONTROL pin
scwioghrinncaehlrgafrceernqoesursaetnRecEsyiasovffiol7teltkareHgdzebteoyrrraoenrdsuRicgCennathel eatwceorfofrekscswtRiothEf.
The error
a typical
switching
noise. The filtered error signal is compared with the internal
oscillator sawtooth waveform to generate the duty cycle
waveform. As the control current increases, the duty cycle
decreases. A clock signal from the oscillator sets a latch
which turns on the output MOSFET. The pulse width modu-
lator resets the latch, turning off the output MOSFET. The
maximum duty cycle is set by the symmetry of the internal
oscillator. The modulator has a minimum ON-time to keep
the current consumption of the TOPSwitch independent
of the error signal. Note that a minimum current must be
driven into the CONTROL pin before the duty cycle begins to
change.
Gate Driver
The gate driver is designed to turn the output MOSFET on at
a controlled rate to minimize common-mode EMI. The gate
drive current is trimmed for improved accuracy.
Error Amplifier
The shunt regulator can also perform the function of an er-
ror amplifier in primary feedback applications. The shunt
regulator voltage is accurately derived from the temperature
compensated bandgap reference. The gain of the error
amplifier is set by the CONTROL pin dynamic impedance.
vTohletaCgOe NleTvRelO. LThpeinCcOlaNmTpRsOeLxtpeirnnaclucrrirecnutitinsiegxncaelssstoofththeeVC
supply current is separated by the shunt regulator and flows
through RE as a voltage error signal.
Cycle-By-Cycle Current Limit
The cycle by cycle peak drain current limit circuit uses the
output MOSFET ON-resistance as a sense resistor. A current
limit comparator compares the output MOSFET ON-state
dadnrraadiinnt-ucsrounursrretchneet vcooauluttapsgeuest ,MVVDODSS(SO(ONFN)E)tTwo ioethfxfcauentehtdirletthshheeostlhdtarervtosohltfaotglhdeev. noHeltaxigtghe
clock cycle. The current limit comparator threshold voltage
is temperature compensated to minimize variation of the
effective peak current limit due to temperature related
changes in output MOSFET RDS(ON).
4
Rev. G 08/16
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4페이지










TOP222YN 전자부품, 판매, 대치품
TOP221-227
L2
22 mH
C6
0.1 µF
250 VAC
BR1
400 V
C1
47 µF
400 V
F1
J1 3.15 A
L
N
VR1
P6KE200
D1
BYV26C
TOPSwitch-II
D U1
CONTROL
TOP224P
C
S
R3
6.8
C5
47 µF
T1
Figure 8. Schematic Diagram of a 20 W Universal Input TOPSwitch-II Power Supply using an 8 lead PDIP.
D2
MUR420
C2
330 µF
35 V
L1
3.3 µH
C3
220 µF
35 V
D3
1N4148
C4
0.1 µF
R1
100
U2
PC817A
R2
220
C7
1 nF
250 VAC
Y1
VR2
1N5241B
11 V
+12 V
RTN
PI-2019-033197
20 W Universal Supply using 8 Lead PDIP
Figure 8 shows a 12 V, 20 W secondary regulated flyback
power supply using the TOP224P in an eight lead PDIP
package and operating from universal 85 to 265 VAC input
voltage. This example demonstrates the advantage of the
higher power 8 pin leadframe used with the TOPSwitch-II
family. This low cost package transfers heat directly to the
board through six source pins, eliminating the heatsink and
the associated cost. Efficiency is typically 80% at low line
input. Output voltage is directly sensed by optocoupler U2
and Zener diode VR2. The output voltage is determined by
the Zener diode (VR2) voltage and the voltage drops across
the optocoupler (U2) LED and resistor R1. Other output
voltages are possible by adjusting the transformer turns ratio
and value of Zener diode VR2.
AC power is rectified and filtered by BR1 and C1 to create
the high voltage DC bus applied to the primary winding of
T1. The other side of the transformer primary is driven by
the integrated TOPSwitch-II high-voltage MOSFET. D1 and
VR1 clamp leading-edge voltage spikes caused by trans-
former leakage inductance. The power secondary winding
is rectified and filtered by D2, C2, L1, and C3 to create the
12 V output voltage. R2 and VR2 provide a slight pre-load
on the 12 V output to improve load regulation at light loads.
The bias winding is rectified and filtered by D3 and C4 to
create a TOPSwitch bias voltage. L2 and Y1-safety capaci-
tor C7 attenuate common mode emission currents caused
by high-voltage switching waveforms on the DRAIN side of
the primary winding and the primary to secondary capaci-
tance. Leakage inductance of L2 with C1 and C6 attenu-
ates differential-mode emission currents caused by the
fundamental and harmonics of the trapezoidal or triangular
primary current waveform. C5 filters internal MOSFET gate
drive charge current spikes on the CONTROL pin, deter-
mines the auto-restart frequency, and together with R1 and
R3, compensates the control loop.
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7
Rev. G 08/16

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부품번호상세설명 및 기능제조사
TOP222Y

Three-terminal Off-line PWM Switch

Power Integrations  Inc.
Power Integrations Inc.
TOP222YN

Three-Terminal Off-Line PWM Switch

Power Integrations
Power Integrations

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