PDF BSC9131 Data sheet ( Hoja de datos )

Número de pieza	BSC9131
Descripción	QorIQ Qonverge Multicore Baseband Processor
Fabricantes	Freescale Semiconductor
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Freescale Semiconductor Data Sheet: Technical Data BSC9131 QorIQ Qonverge Multicore Baseband Processor Document Number: BSC9131 Rev. 1, 08/2015 BSC9131 FC-PBGA–520 21 mm x 21 mm The following list provides an overview of the feature set: • High-performance 32-bit e500 core built on Power Architecture® technology: – 36-bit physical addressing – Double-precision floating-point support – 32-Kbyte L1 instruction cache and 32-Kbyte L1 data cache – Enhanced hardware and software debug support – 800 MHz/1 GHz clock frequency – 256-Kbyte L2 cache with ECC; also configurable as SRAM and stashing memory • One SC3850 core subsystem, which connects to the following: – 32 Kbyte 8-way level 1 data/instruction cache (L1 Dcache/ICache) – 512 Kbyte 8-way level 2 unified instruction/data cache (L2 cache/M2 memory) – Memory management unit (MMU) – Enhanced programmable interrupt controller (EPIC) – Debug and profiling unit (DPU) – Two 32-bit quad timers • Multi Accelerator Platform Engine for Femto Base Station Baseband Processing (MAPLE-B2F) – Supports variable sizes in Fourier Transforms, Convolution, Filtering, Turbo, Viterbi, Chiprate – Consists of accelerators for UMTS chip rate processing, LTE UP/DL channel processing, Matrix Inversion operations, and CRC algorithms • DDR3/DDR3L SDRAM memory controller supports 32-bit without ECC and 16-bit with ECC • Integrated security engine (ULE CAAM) – Protocol support includes DES, AES, RNG, CRC, MDE, PKE, SHA, and MD5 • Secure boot capability • Two enhanced three-speed Ethernet controllers (eTSECs) – 10/100/1000 Mbps support – TCP/IP acceleration, quality of service, and classification capabilities – IEEE Std 1588™ support – eTSEC1 supports RGMII and RMII interfaces – eTSEC2 supports an RGMII interface • High-speed USB controller (USB 2.0) – Host and device support – Enhanced host controller interface (EHCI) – ULPI interface • Enhanced secure digital (SD/MMC) host controller (eSDHC) • Integrated Flash controller (IFC), supporting NAND, NOR, and general ASIC • TDM with one TDM port • Antenna interface controller (AIC), supporting three industry standard JESD/three custom parallel RF interfaces (two dual and one single port) and three MAXIM's MaxPHY serial interfaces • Universal Subscriber Identity Module (USIM) interface – Facilitates communication to SIM cards or Eurochip pre-paid phone cards • Four enhanced serial peripheral interfaces (eSPI) • Programmable interrupt controller (PIC) compliant with OpenPIC standard • One four-channel DMA controller • Two I2C interfaces • Two dual UART (DUART) interfaces • Two pulse-width modulator (PWM) interfaces • 96 general-purpose I/O signals • Eight 32-bit timers • Operating temperature (Ta - Tj) range: 0–105° C © 2014-2015 Freescale Semiconductor, Inc. All rights reserved. 1 page Figure 3 shows detailed view A. Pin Assignments DETAIL A 1 2 3 4 5 6 7 8 9 10 11 12 13 A TDO B SYSCLK BVDD_ VSEL01 TDI VSS SCAN_ MODE_ B TEST_ SEL_B OVDD IIC1_ SCL UART_ RTS_ B00 UART_ SIN00 READY HRESET _B IFC_ AD09 UART_ SIN01 EE1 VSS UDE_ B IFC_ AD00 IFC_ AD04 VSS IFC_ IFC_ AD10 ADDR21 IFC_ AD05 IFC_ AD06 C XVDD2_ XVDD1_ TRST_B VSEL VSEL IIC1_ SDA CVDD_ VSEL UART_ RTS_ B01 RTC TMP_ EE0 DETECT IFC_ AD11 IFC_ AD01 IFC_ AD03 D MCS_B02 VSS TCK TMS CFG_ 1_JTAG _MODE LVDD_ VSEL VSS UART_ CTS_ B00 MAX_ REF_ CLK VSS IFC_ AD12 IFC_ AD02 E MA13 MA15 DDRCLK VSS UART_ SOUT01 OVDD CFG_0_ UART_ JTAG_ CTS_ MODE B01 OVDD DSP_ HRESET_ BVDD CLKIN REQ_B IFC_ AD15 VSS IFC_ AD08 F MA08 MA06 MA02 MCS_ B03 UART_ SOUT00 G MA11 VSS MA09 MA01 MA05 H MA14 MBA00 MA07 MBA01 GVDD J MCKE01 MA12 MA04 VSS MA03 AVDD_ OVDD DDR OVDD BVDD_ VSEL00 BVDD BVDD GVDD VDDC VSS VDDC VSS VDDC K MCS_B01 VSS MBA02 MCS_ B00 MA00 L MA10 MODT01 MODT00 MCKE00 GVDD GVDD VSS VDDC VSS VDDC VSS POVDD2 VDDC VSS VDDC VSS VDDC M MCAS_B MWE_B MCK_B VSS MDIC00 MVREF VSS VDDC VSS VDDC VSS N MDM01 VSS MCK MRAS_B MDIC01 POVDD1 VDDC VSS VDDC VSS VDDC Figure 3. Ball Layout Diagram—Detail A BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1 Freescale Semiconductor 5 5 Page Signal MCS_B02 MCS_B03 MCKE00 MCKE01 MCK MCK_B MODT00 MODT01 MDIC00 MDIC01 EC_MDC EC_MDIO TSEC1_TXD00 TSEC1_TXD01 TSEC1_TXD02 TSEC1_TXD03 TSEC1_TX_EN TSEC1_RXD00 TSEC1_RXD01 TSEC1_RXD02 TSEC1_RXD03/ TSEC1_RX_ER TSEC1_RX_DV TSEC1_RX_CLK TSEC1_GTX_CLK TSEC1_GTX_CLK125/ TSEC1_TX_CLK TSEC1_TXD00 TSEC1_TXD01 TSEC1_TX_EN TSEC1_RXD00 TSEC1_RXD01 Table 1. BSC9131 Pinout Listing (continued) Signal Description Chip Select Chip Select Clock Enable Clock Enable Clock Clock Complements On Die Termination On Die Termination Driver Impedence Calibration Driver Impedence Calibration Ethernet Management Management Data Clock Management Data In/Out eTSEC 1 (RGMII) RGMII Transmit Data RGMII Transmit Data RGMII Transmit Data RGMII Transmit Data RGMII Transmit Enable RGMII Receive Data RGMII Receive Data RGMII Receive Data RGMII Receive Data Pin Number D1 F4 L4 J1 N3 M3 L3 L2 M5 N5 Pin Type O O O O O O O O I/O I/O AE18 AD16 O I/O AE11 AC10 AC12 AE15 AB12 AE13 AC14 AD13 AA12 O O O O O I I I I Pin Assignments Power Supply GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD VSS GVDD Note — — — — — — — — 17 17 LVDD LVDD 2 18 LVDD LVDD LVDD LVDD LVDD LVDD LVDD LVDD LVDD 2 2 2 2 — — — — — RGMII Receive Data Valid RGMII Receive Clock RGMII Transmit Clock Out RGMII Reference Clock AC13 AA13 AD11 AD14 I I O I LVDD LVDD LVDD LVDD — — — — eTSEC 1 (RMII) RMII Transmit Data RMII Transmit Data RMII Transmit Data Valid RMII Receive Data RMII Receive Data AE11 AC10 AB12 AE13 AC14 O O O I I LVDD LVDD LVDD LVDD LVDD 2 2 — — — BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1 Freescale Semiconductor 11 11 Page

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