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부품번호 | ICS843S104I-133 기능 |
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기능 | Crystal-to-LVPECL 133MHz Clock Synthesizer | ||
제조업체 | IDT | ||
로고 | |||
Crystal-to-LVPECL 133MHz
Clock Synthesizer
ICS843S104I-133
DATA SHEET
General Description
The ICS843S104I-133 is a PLL-based clock
ICS synthesizer specifically designed for low phase noise
HiPerClockS™ applications. This device generates a 133.33MHz
differential LVPECL clock from an input reference of
25MHz. The input reference may be derived from an
external source or by the addition of a 25MHz crystal to the on-chip
crystal oscillator. An external reference is applied to the PCLK,
nPCLK pins.The device offers spread spectrum clock output for
reduced EMI applications. An I2C bus interface is used to enable or
disable spread spectrum operation as well as to select either a down
spread value of -0.35% or -0.5%.The ICS843S104I-133 is available
in a lead-free 32-Lead VFQFN package.
Features
• Four LVPECL output pairs
• Crystal oscillator interface: 25MHz
• Differential PCLK/nPCLK input pair
• PCLK/nPCLK supports the following input types: LVPECL, CML,
SSTL
• Output frequency: 133.33MHz
• PCI Express (2.5 Gb/s) and Gen 2 (5 Gb/S) jitter compliant
• RMS phase jitter @ 133.33MHz (12kHz – 20MHz):
1.2ps (typical)
• I2C support with readback capabilities up to 400kHz
• Spread Spectrum for electromagnetic interference (EMI) reduction
• 3.3V operating supply mode
• -40°C to 85°C ambient operating temperature
• Available lead-free (RoHS 6) package
Block Diagram
REF_SEL Pulldown
PCLK Pulldown
nPCLK Pullup/Pulldown
25MHz
XTAL_IN
OSC
XTAL_OUT
SDATA Pullup
SCLK Pullup
1
PLL
0
I2C
Logic
4
Q[1:4]
4
nQ[1:4]
Pin Assignment
32 31 30 29 28 27 26 25
VCC 1
24 VEE
REF_SEL 2
23 nQ3
VEE 3
22 Q3
PCLK 4
21 VCC
nPCLK 5
20 VEE
VEE 6
19 nQ4
VCCA 7
18 Q4
VEE 8
17 VCC
9 10 11 12 13 14 15 16
ICS843S104I-133
32-Lead VFQFN
5.0mm x 5.0mm x 0.925mm
package body
K Package
Top View
ICS843S104BKI-133 REVISION A JUNE 9, 2009
1
©2009 Integrated Device Technology, Inc.
ICS843S104I-133 Data Sheet
CRYSTAL-TO-LVPECL 133MHZ CLOCK SYNTHESIZER
Table 3B. Block Read and Block Write Protocol
Bit Description = Block Write
1 Start
2:8 Slave address - 7 bits
9 Write
10 Acknowledge from slave
11:18
Command Code - 8 bits
19 Acknowledge from slave
20:27
Byte Count - 8 bits
28 Acknowledge from slave
29:36
Data byte 1 - 8 bits
37 Acknowledge from slave
38:45
Data byte 2 - 8 bits
46 Acknowledge from slave
Data Byte/Slave Acknowledges
Data Byte N - 8 bits
Acknowledge from slave
Stop
Bit
1
2:8
9
10
11:18
19
20
21:27
28
29
30:37
38
39:46
47
48:55
56
Description = Block Read
Start
Slave address - 7 bits
Write
Acknowledge from slave
Command Code - 8 bits
Acknowledge from slave
Repeat start
Slave address - 7 bits
Read = 1
Acknowledge from slave
Byte Count from slave - 8 bits
Acknowledge
Data Byte 1 from slave - 8 bits
Acknowledge
Data Byte 2 from slave - 8 bits
Acknowledge
Data Bytes from Slave/Acknowledge
Data Byte N from slave - 8 bits
Not Acknowledge
Stop
Table 3C. Byte Read and Byte Write Protocol
Bit Description = Byte Write
1 Start
2:8 Slave address - 7 bits
9 Write
10 Acknowledge from slave
11:18
Command Code - 8 bits
19 Acknowledge from slave
20:27
Data byte - 8 bits
28 Acknowledge from slave
29 Stop
Bit
1
2:8
9
10
11:18
19
20
21:27
28
29
30:37
38
39
Description = Byte Read
Start
Slave address - 7 bits
Write
Acknowledge from slave
Command Code - 8 bits
Acknowledge from slave
Repeat start
Slave address - 7 bits
Read
Acknowledge from slave
Data from slave - 8 bits
Not Acknowledge
Stop
ICS843S104BKI-133 REVISION A JUNE 9, 2009
4
©2009 Integrated Device Technology, Inc.
4페이지 ICS843S104I-133 Data Sheet
CRYSTAL-TO-LVPECL 133MHZ CLOCK SYNTHESIZER
Table 4B. LVCMOS/LVTTL DC Characteristics, VCC = 3.3V ± 5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
VIH Input High Voltage SDATA, SCLK
VIL Input Low Voltage SDATA, SCLK
SDATA, SCLK
IIH Input High Current
REF_SEL
SDATA, SCLK
IIL Input Low Current
REF_SEL
VCC = VIN = 3.465V
VCC = VIN = 3.465V
VCC = 3.465V, VIN = 0V
VCC = 3.465V, VIN = 0V
2.0
1.7
-150
-10
Typical
Maximum
VCC + 0.3
VCC + 0.3
10
150
Units
V
V
µA
µA
µA
µA
Table 4C. LVPECL DC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C)
Symbol Parameter
Test Conditions
Minimum
IIH
IIL
VPP
VCMR
VOH
VOL
VSWING
Input High Current
PCLK, nPCLK
Input Low Current
PCLK
nPCLK
Peak-to-Peak Voltage; NOTE 1
Common Mode Input Voltage; NOTE 1, 2
Output High Voltage; NOTE 3
Output Low Voltage; NOTE 3
Peak-to-Peak Output Voltage Swing
VCC = VIN = 3.465V
VCC = 3.465V, VIN = 0V
VCC = 3.465V, VIN = 0V
-10
-150
0.3
VEE + 1.5
VCC – 1.3
VCC – 2.0
0.6
NOTE 1: VIL should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined as VIH.
NOTE 3: Outputs terminated with 50Ω to VCC – 2V.
Typical
Maximum
150
1.0
VCC
VCC – 0.8
VCC – 1.6
1.0
Units
µA
µA
µA
V
V
V
V
V
Table 5. Crystal Characteristics
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Test Conditions
NOTE: Characterized using an 18pF parallel resonant crystal.
Minimum Typical Maximum
Fundamental
25
50
7
Units
MHz
Ω
pF
ICS843S104BKI-133 REVISION A JUNE 9, 2009
7
©2009 Integrated Device Technology, Inc.
7페이지 | |||
구 성 | 총 24 페이지수 | ||
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부품번호 | 상세설명 및 기능 | 제조사 |
ICS843S104I-133 | Crystal-to-LVPECL 133MHz Clock Synthesizer | IDT |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |