Datasheet.kr   

ICS843S1333 데이터시트 PDF




IDT에서 제조한 전자 부품 ICS843S1333은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


PDF 형식의 ICS843S1333 자료 제공

부품번호 ICS843S1333 기능
기능 CRYSTAL-TO-3.3V LVPECL CLOCK SYNTHESIZER
제조업체 IDT
로고 IDT 로고


ICS843S1333 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.




전체 13 페이지수

미리보기를 사용할 수 없습니다

ICS843S1333 데이터시트, 핀배열, 회로
CRYSTAL-TO-3.3V LVPECL CLOCK SYNTHESIZER
ICS843S1333
General Description
The ICS843S1333 is a high frequency clock
ICS generator and is a member of the HiPerClockS™
HiPerClockS™ family of High Performance Clock Solutions from
IDT. The ICS843S1333 uses an external 20MHz
crystal to synthesize 1333.33MHz. The
ICS843S1333 has excellent cycle-to-cycle and RMS period jitter
performance.
The ICS843S1333 operates at 3.3V operating supply and is
available in a fully RoHS compliant 8-lead TSSOP package.
Features
One differential LVPECL output
Crystal oscillator interface designed for 18pF, 20MHz parallel
resonant crystal
Cycle-to-Cycle Jitter: 25ps (maximum)
Period Jitter, RMS: 2ps (maximum)
Output Duty Cycle: 48 – 52%
Full 3.3V supply mode
0°C to 70°C ambient operating temperature
Available in lead-free (RoHS 6) packages
Table 1. Frequency Table
Crystal Frequency (MHz)
20
Multiplier Value
66.67
Output Frequency (MHz)
1333.33
Block Diagram
OE Pullup
20MHz
XTAL_IN
OSC
XTAL_OUT
PLL Multiplier
(x66.67)
DQ
CLK
Pin Assignment
VCCA 1
8 VCC
VEE 2
7Q
Q
XTAL_OUT 3
6 nQ
XTAL_IN 4
5 OE
nQ
ICS843S1333
8 Lead TSSOP
4.40mm x 3.0mm x 0.925mm package body
G Package
Top View
IDT™ / ICS™ 3.3V LVPECL CLOCK SYNTHESIZER
1
ICS843S1333CG REV. A AUGUST 28, 2008




ICS843S1333 pdf, 반도체, 판매, 대치품
ICS843S1333
CRYSTAL-TO-3.3V LVPECL CLOCK SYNTHESIZER
Table 5. Crystal Characteristics
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Test Conditions
Minimum Typical Maximum
Fundamental
20
50
7
Units
MHz
pF
AC Electrical Characteristics
Table 6. AC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, TA = 0°C to 70°C
Parameter Symbol
Test Conditions
fOUT
tjit(cc)
Output Frequency
Cycle-to-Cycle Jitter; NOTE 1
tjit(per)
Period Jitter, RMS; NOTE 1
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
NOTE 1: This parameter is defined in accordance with JEDEC Standard 65.
Minimum
100
48
Typical
1333.33
Maximum
25
2
200
52
Units
MHz
ps
ps
ps
%
IDT™ / ICS™ 3.3V LVPECL CLOCK SYNTHESIZER
4
ICS843S1333CG REV. A AUGUST 28, 2008

4페이지










ICS843S1333 전자부품, 판매, 대치품
ICS843S1333
CRYSTAL-TO-3.3V LVPECL CLOCK SYNTHESIZER
LVCMOS to XTAL Interface
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 3. The XTAL_OUT pin can be left floating. The
input edge rate can be as slow as 10ns. For LVCMOS signals, it is
recommended that the amplitude be reduced from full swing to half
swing in order to prevent signal interference with the power rail and
to reduce noise. This configuration requires that the output
impedance of the driver (Ro) plus the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination
at the crystal input will attenuate the signal in half. This can be
done in one of two ways. First, R1 and R2 in parallel should equal
the transmission line impedance. For most 50applications, R1
and R2 can be 100. This can also be accomplished by removing
R1 and making R2 50.
VCC
VCC
R1
Ro Rs 50
0.1µf
XTAL_IN
Zo = Ro + Rs
R2
XTAL_OUT
Figure 3. General Diagram for LVCMOS Driver to XTAL Input Interface
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50
transmission lines. Matched impedance techniques should be
used to maximize operating frequency and minimize signal
distortion. Figures 4A and 4B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and
clock component process variations.
FOUT
Zo = 50
FIN
Zo = 50
50
RTT =
1
((VOH + VOL) / (VCC – 2)) – 2
Zo
50
VCC - 2V
RTT
Figure 4A. 3.3V LVPECL Output Termination
IDT™ / ICS™ 3.3V LVPECL CLOCK SYNTHESIZER
FOUT
3.3V
125
125
Zo = 50
FIN
Zo = 50
84
84
Figure 4B. 3.3V LVPECL Output Termination
7 ICS843S1333CG REV. A AUGUST 287, 2008

7페이지


구       성 총 13 페이지수
다운로드[ ICS843S1333.PDF 데이터시트 ]

당사 플랫폼은 키워드, 제품 이름 또는 부품 번호를 사용하여 검색할 수 있는

포괄적인 데이터시트를 제공합니다.


구매 문의
일반 IC 문의 : 샘플 및 소량 구매
-----------------------------------------------------------------------

IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한
광범위한 전력 반도체를 판매합니다.

전력 반도체 전문업체

상호 : 아이지 인터내셔날

사이트 방문 :     [ 홈페이지 ]     [ 블로그 1 ]     [ 블로그 2 ]



관련 데이터시트

부품번호상세설명 및 기능제조사
ICS843S1333

CRYSTAL-TO-3.3V LVPECL CLOCK SYNTHESIZER

IDT
IDT
ICS843S1333D

Crystal-to-3.3V LVPECL Clock Synthesizer

IDT
IDT

DataSheet.kr       |      2020   |     연락처      |     링크모음      |      검색     |      사이트맵