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HI-8502 데이터시트 PDF




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부품번호 HI-8502 기능
기능 ARINC 429 Line Driver
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HI-8502 데이터시트, 핀배열, 회로
July 2016
HI-8500
ARINC 429 Line Driver Family
with Tri-State Option
DESCRIPTION
The HI-8500 family is a full-featured ARINC 429 Line Driver
providing three choices of output resistance and a tri-state
option, which allows the outputs to be put in a high-
impedance state.
Like Holt’s industry-standard HI-8585 and HI-8586 ARINC
429 line drivers, the HI-8500 includes digital slew-rate
selection to support high-speed (100kb/s) and low-speed
(12.5kb/s) data rates.
The part is offered in a variety of small footprint packages
including 5mm x 5mm 20-lead plastic QFN package and
traditional 8-pin SOIC package. Ceramic DIPs are also
available.
Inputs are compatible with either 5V or 3.3V logic. Internal
pull-up/down resistors are available on HI-8506 for each
digital input. The resistors are brought out to pins, which
may be externally grounded to hold the ARINC bus in the
null-sate during system power-up, or connected to logic
power to hold the outputs tri-state. This feature is of benefit
when interfacing to field-programmable logic as it defines a
known-state during FPGA initialization, avoiding transient
bus noise at power-on.
The HI-8500 family offers a pin-for-pin drop-in replacement
for the DEI1070A-DEI1075A, DEI1170A and DEI1171A.
See table 1 for exact part number cross references.
FEATURES
? 0, 10 and 37.5 Ohm outputs
? Tri-state outputs
? Wide power-supply range
? 8kV ESD tolerance
? Digital slew-rate control
? Drop-in alternative to DEI1070A-DEI1075A,
DEI1170A, DEI1171A
? DO-254 certifiable
PIN CONFIGURATIONS
SLP1.5 - 1
TXIN0 - 2
TXIN1 - 3
GND - 4
8 - V+
7 - TXBn
6 - TXAn
5 - V-
HI-8500PSx, HI-8501PSx, HI-8502PSx
HI-8503PSx, HI-8504PSx & HI-8505PSx
8 - PIN Plastic Narrow Body ESOIC
TSEN - 1
-2
-3
V- - 4
TXA37 - 5
15 - SLP1.5
14 - RSLP (*)
13 -
12 - V+
11 - TXB37
(DS8500 Rev. New)
HI-8506PCx, HI-8507PCx
20-pin 5mm x 5mm Chip-Scale Package
(*) Not connected on HI-8506
HOLT INTEGRATED CIRCUITS
www.holtic.com
7/16




HI-8502 pdf, 반도체, 판매, 대치품
HI-8500
PIN DESCRIPTIONS
HI-8500, HI-8501, HI-8502, HI-8503, HI-8504, HI-8505
PIN SYMBOL FUNCTION
DESCRIPTION
1 SLP1.5 Digital Input Slope Control. Set high for 1.5us output rise/fall time. Set low for 10us rise/fall time.
2 TXIN0 Digital Input Negative data input. See truth table, figure 2.
3 TXIN1 Digital Input Positive data input. See truth table, figure 2.
4
GND
Power supply Ground
5 V- Power supply Negative supply pin. -9.5V to -16.5V
6
TXAn
Analog output ARINC 429 bus positive output with nΩ internal resistor
7
TXBn
Analog output ARINC 429 bus negative output with nΩ internal resistor
8 V+ Power supply Positive supply pin. +9.5V to +16.5V
HI-8506, HI-8507
PIN SYMBOL FUNCTION
DESCRIPTION
1 TSEN Digital Input Enables tri-state option. See truth table, figure 2. Internal 250k pull-up to 5V.
2-
- Not connected
3-
- Not connected
4 V- Power supply Negative supply pin. -9.5V to -16.5V
5 TXA37 Analog output ARINC 429 bus positive output with 37.5Ω internal resistor
6 TXA10 Analog output ARINC 429 bus positive output with 10Ω internal resistor
7
TXA0
Analog output ARINC 429 bus positive output with 0Ω internal resistor
8-
- Not connected
9
TXB0
Analog output ARINC 429 bus negative output with 0Ω internal resistor
10 TXB10 Analog output ARINC 429 bus negative output with 10Ω internal resistor
11 TXB37 Analog output ARINC 429 bus negative output with 37.5Ω internal resistor
12 V+ Power supply Positive supply pin. +9.5V to +16.5V
13 RIN1 Pull-up/down 50KΩ internal connection to TXIN1. May be connected to GND, VDD or left floating.
14 RSLP Pull-up/down 50KΩ internal connection to SLP1.5. May be connected to GND, VDD or left floating.
15 SLP1.5
Digital Input Slope Control. Set high for 1.5us output rise/fall time. Set low for 10us rise/fall time.
16 RIN0 Pull-up/down 50KΩ internal connection to TXIN0. May be connected to GND, VDD or left floating.
17 TXIN0
Digital Input Negative data input. See truth table, figure 2.
18 TXIN1
Digital Input Positive data input. See truth table, figure 2.
19 GND Power supply Ground
20 -
- Not connected
Note: Pins 13, 14 and 16 are not connected for HI-8506.
HOLT INTEGRATED CIRCUITS
4

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HI-8502 전자부품, 판매, 대치품
HI-8500
DC ELECTRICAL CHARACTERISTICS
V+/V- = +/- 9.5V to +/- 16.5V, TA = Operating Temperature Range (unless otherwise stated)
PARAMETERS
SYMBOL
TEST CONDITIONS
MIN TYP MAX UNITS
Input voltage (Logic Inputs)
high
low
VIH
VIL
2.0 - V+ V
-0.3 - 0.8 V
Input current (TX1IN, TX0IN, SLP1.5)
source
sink
IIH
IIL
VIN = 5V
VIN = 0V
0 - 1.0 μA
-1.0 - 0 μA
Input current (TSEN)
source
sink
IIH
VIN = 5V
0 - 1.0 μA
IIL
VIN = 0V
-100
-
0
μA
ARINC output voltage (Differential)
one
zero
null
VDIFF1
VDIFF0
VDIFFN
no load; TXAn - TXBn
no load; TXAn - TXBn
no load; TXAn - TXBn
9.00 10.00 11.00
-11.00 -10.00 -9.00
-0.50 0 0.50
V
V
V
ARINC output voltage (Ref. to GND)
one or zero
null
VDOUT
VNOUT
no load & magnitude at pin 4.50
no load
-0.25
5.00 5.50
0 0.25
V
V
Output Tristate Leakage Current
IOZ
VOUT = -10V to +10V
-100
+100 μA
ARINC Output Short Circuit Current
(TXA0 or TXB0 pin)
Output Low
Output High
ISCLO
ISCHI
External 37.5Ω to GND
100 133 146
-146 -133 -100
mA
mA
Output Resistance
TXA37, TXB37
TXA10, TXB10
TXA0, TXB0
ROUT37
ROUT10
ROUT0
See Figure 5.
35 37.5 40
7.5 10 12.5
0 0.2 2.0
Ω
Ω
Ω
Operating supply current
IV+
IV-
SLP1.5 = V+
IDD TX1IN & TX0IN = 0V: no load -
3.0 6.0
IEE TX0IN & TX1IN = 0V: no load -6.0 -2.5
-
mA
mA
HOLT INTEGRATED CIRCUITS
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