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What is HI-8507?

This electronic component, produced by the manufacturer "HOLTIC", performs the same function as "ARINC 429 Line Driver".


HI-8507 Datasheet PDF - HOLTIC

Part Number HI-8507
Description ARINC 429 Line Driver
Manufacturers HOLTIC 
Logo HOLTIC Logo 


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July 2016
HI-8500
ARINC 429 Line Driver Family
with Tri-State Option
DESCRIPTION
The HI-8500 family is a full-featured ARINC 429 Line Driver
providing three choices of output resistance and a tri-state
option, which allows the outputs to be put in a high-
impedance state.
Like Holt’s industry-standard HI-8585 and HI-8586 ARINC
429 line drivers, the HI-8500 includes digital slew-rate
selection to support high-speed (100kb/s) and low-speed
(12.5kb/s) data rates.
The part is offered in a variety of small footprint packages
including 5mm x 5mm 20-lead plastic QFN package and
traditional 8-pin SOIC package. Ceramic DIPs are also
available.
Inputs are compatible with either 5V or 3.3V logic. Internal
pull-up/down resistors are available on HI-8506 for each
digital input. The resistors are brought out to pins, which
may be externally grounded to hold the ARINC bus in the
null-sate during system power-up, or connected to logic
power to hold the outputs tri-state. This feature is of benefit
when interfacing to field-programmable logic as it defines a
known-state during FPGA initialization, avoiding transient
bus noise at power-on.
The HI-8500 family offers a pin-for-pin drop-in replacement
for the DEI1070A-DEI1075A, DEI1170A and DEI1171A.
See table 1 for exact part number cross references.
FEATURES
? 0, 10 and 37.5 Ohm outputs
? Tri-state outputs
? Wide power-supply range
? 8kV ESD tolerance
? Digital slew-rate control
? Drop-in alternative to DEI1070A-DEI1075A,
DEI1170A, DEI1171A
? DO-254 certifiable
PIN CONFIGURATIONS
SLP1.5 - 1
TXIN0 - 2
TXIN1 - 3
GND - 4
8 - V+
7 - TXBn
6 - TXAn
5 - V-
HI-8500PSx, HI-8501PSx, HI-8502PSx
HI-8503PSx, HI-8504PSx & HI-8505PSx
8 - PIN Plastic Narrow Body ESOIC
TSEN - 1
-2
-3
V- - 4
TXA37 - 5
15 - SLP1.5
14 - RSLP (*)
13 -
12 - V+
11 - TXB37
(DS8500 Rev. New)
HI-8506PCx, HI-8507PCx
20-pin 5mm x 5mm Chip-Scale Package
(*) Not connected on HI-8506
HOLT INTEGRATED CIRCUITS
www.holtic.com
7/16

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HI-8507 equivalent
HI-8500
FUNCTIONAL DESCRIPTION
Figure 2 is a block diagram of the line driver. The +5V and
-5V levels are generated from the supply voltages. Output
slope control is set by on-chip precision current sources
and capacitors.
The TXIN0 and TXIN1 inputs receive logic signals from a
control transmitter chip such as the HI-3210 or FPGA.
TXAn and TXBn hold each side of the ARINC bus at
Ground until one of the inputs becomes a One. If for ex-
ample TXIN1 goes high, a charging path is enabled to 5V
on an “A” side internal capacitor while the “B” side is en-
abled to -5V. The charging current is selected by the
SLP1.5 pin. If the SLP1.5 pin is high, the capacitor is
nominally charged from 10% to 90% in 1.5μs. If SLP1.5 is
low, the rise and fall times are 10μs.
A unity gain buffer receives the internally generated slopes
and differentially drives the ARINC line. Current is limited
by the series output resistors at each pin. There are no
fuses at the outputs of the HI-8500.
ARINC 429 requires that each line has a source imped-
ance of 37.5 Ohms. The TXA37 and TXB37 have the re-
quired resistance to directly drive the bus. Alternatively,
TXA/B10 or TXA/B0 outputs have 10 ohms or zero ohms
internally. The reduced resistance allows for external light-
ning protection circuitry to be added, while maintaining the
total output resistance at 37.5 Ohms. See Holt Applica-
tions Notes AN-300 and AN-301 for suitable, proven light-
ning protection schemes.
The HI-8500 is built using high-speed CMOS technology.
Care should be taken to ensure the V+ and V- supplies are
locally decoupled.
TX0IN
TX1IN
ESD
PROTECTION
AND
VOLTAGE
TRANSLATION
ONE
NULL
ZERO
CONTROL
LOGIC
5V “A” SIDE
CURRENT
CONTROL
-5V
SLP1.5
ZERO
NULL
5V “B” SIDE
CURRENT
CONTROL
ONE
CONTROL
LOGIC
-5V
FIGURE 2 - LINE DRIVER BLOCK DIAGRAM
TXAOUT
TXBOUT
APPLICATION INFORMATION
Figure 3 shows a possible application
of the HI-8500 interfacing an ARINC 429
transmit channel from the HI-3200.
HARDWIRED
OR
{
DRIVEN FROM LOGIC
ARINC
Channel
ARINC
Channel
5V
1
2
VCC
TESTA
ROUTA
6
8
TESTB
7
ROUTB
4 HI-8450
RINA
3
RINB
5
12V
8
6 TXA37
V+
TXIN1
7 HI-8500
TXB37
TXIN0
GND
SLP1.5
V-
45
3
2
1
ARX0P
ARX0N
HI-3200
HOST SPI
ATX0P
ATX0N
ATXSLP0
-12V
FIGURE 3 - APPLICATION DIAGRAM
HOLT INTEGRATED CIRCUITS
5


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